Boosting transistor performance with non-rectangular channels

Abstract

Roughly described, the invention includes layouts and masks for an integrated circuit, in which the diffusion shape for a transistor includes a transversely extending jog on one or both transversely opposite sides, the jog having inner and outer corners, at least one of which is located relative to the gate conductor longitudinally such that during lithographic printing of the diffusion shape onto the integrated circuit, the corner will round and extend at least partly into the channel region. The invention also includes aspects for a system and method for introducing such jogs, and for an integrated circuit device having a non-rectangular channel region, the channel region being wider where it meets the source region than at some other longitudinal position under the gate.

1 . A lithographic mask set including one or more masks for use in forming in an integrated circuit, the mask set having shapes for defining a channel region for a transistor, a gate conductor overlying the channel region, and first and second diffusion regions on longitudinally opposite sides of the channel region, the first and second diffusion regions being of a first doping type and the channel region being of a second doping type opposite the first doping type, the first and second diffusion regions being connected in a circuit as respectively first and second current path terminals of the transistor,
 the mask set including a first shape for defining a geometric union of the channel region and the first and second diffusion regions, and a second shape for defining the gate conductor, the second shape crossing the first shape transversely, for use in a process in which the channel region is doped before the gate conductor is applied to the integrated circuit using the second shape, and the first and second diffusion regions are doped after the gate conductor is applied,   wherein the first shape has transversely opposite first and second longitudinal sides along the length of the first diffusion region,   and wherein the first shape includes a first transversely extending jog on the first longitudinal side of the first shape, the first jog having an inner corner and an outer corner, the first jog being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, at least one of the inner and outer corners will round and extend at least partly within the channel region.   
     
     
         2 . A lithographic mask set according to  claim 1 , wherein the first shape further includes a second transversely extending jog on the first side of the first shape on the same side of the second shape longitudinally as the second diffusion region, the second jog having an inner corner proximal to the second shape, the second jog being located sufficiently near the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the inner corner of the second jog will round so as to at least partially underlie the gate conductor. 
     
     
         3 . A lithographic mask set according to  claim 1 , wherein the mask set further connects the first diffusion region as the source of the transistor. 
     
     
         4 . A lithographic mask set according to  claim 3 , wherein the first shape includes no transversely extending second jog on the same side of the second shape longitudinally as the second diffusion region, which second jog is located so near to the second shape longitudinally that during lithographic printing, the inner corner of the second jog will round and at least partially underlie the gate conductor. 
     
     
         5 . A lithographic mask set according to  claim 1 , wherein the first shape further includes a second transversely extending jog on the second longitudinal side of the first shape, the second jog having an inner corner and an outer corner, the second jog being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, at least one of the inner and outer corners of the second jog will round and extend at least partly within the channel region. 
     
     
         6 . A lithographic mask set according to  claim 1 , wherein the first jog is located on the same side of the second shape longitudinally as the first diffusion region, and is located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the inner corner of the first jog will round and extend at least partly into the channel region. 
     
     
         7 . A lithographic mask set according to  claim 1 , wherein the first jog is located on the same side of the second shape longitudinally as the second diffusion region, and is located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the outer corner of the first jog will round and extend at least partly into the channel region. 
     
     
         8 . A lithographic mask set according to  claim 1 , wherein the first jog is located at a longitudinal position which overlaps with the second shape longitudinally, such that during lithographic printing of the first shape onto the integrated circuit, both the inner and outer corners of the first jog will round and be disposed at least partly within the channel region. 
     
     
         9 . A lithographic mask set according to  claim 1 , wherein the first jog is located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the outer corner of the first jog will round and extend at least partly within the channel region,
 and wherein the first shape further includes a second transversely extending jog on the first longitudinal side of the first shape, the second jog having an inner corner and an outer corner, the second jog being located relative to the first jog such that the inner corner of the second jog is transversely proximal to the outer corner of the first jog, the second jog being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the inner corner of the second jog will round and extend at least partly within the channel region.   
     
     
         10 . A lithographic mask set including one or more masks for use in forming in an integrated circuit, the mask set having shapes for defining first and second channel regions for respective first and second transistors, first and second gate conductors overlying respectively the first and second channel regions, first and second diffusion sub-regions on longitudinally opposite sides of the first channel region, and a third diffusion sub-region on the side of the second channel region longitudinally opposite the second diffusion sub-region, the first, second and third diffusion sub-regions being of a first doping type and the first and second channel regions being of a second doping type opposite the first doping type, the first and second diffusion regions being connected in a circuit as respectively first and second current path terminals of the first transistor, and the second and third diffusion regions being connected in a circuit as respectively first and second current path terminals of the second transistor,
 the mask set including a first shape for defining a geometric union of the first and second channel regions and the first, second and third diffusion sub-regions, a second shape for defining the first gate conductor and a third shape for defining the second gate conductor, the second and third shapes each crossing the first shape transversely, for use in a process in which the first and second channel regions are doped before the first and second gate conductors are applied to the integrated circuit using the second and third shapes, and the first, second and third diffusion sub-regions are doped after the first and second gate conductors are applied,   wherein the first shape has transversely opposite first and second sides along the length of the second diffusion region,   and wherein the first shape includes a transversely extending jog on the first side of the first shape, the jog having a first inner corner proximal to the second shape and a second inner corner proximal to the third shape,   the first inner corner of the jog being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the first inner corner will round and extend at least partly within the first channel region,   and the second inner corner of the jog being located relative to the third shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the second inner corner will round and extend at least partly within the second channel region.   
     
     
         11 . A lithographic mask set according to  claim 10 , wherein the first shape further includes a second transversely extending jog on the first side of the first shape and within the first diffusion sub-region, the second jog having an inner corner proximal to the second shape,
 wherein the first shape further includes a third transversely extending jog on the first side of the first shape and within the third diffusion sub-region, the third jog having an inner corner proximal to the third shape,   the inner corner of the second jog being located sufficiently near the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the inner corner of the second jog will round so as to extend at least partly into the first channel region,   and the inner corner of the third jog being located sufficiently near the third shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the inner corner of the third jog will round so as to extend at least partly into the second channel region.   
     
     
         12 . A lithographic mask set according to  claim 10 , wherein the first shape includes no transversely extending second jog within the first and third diffusion sub-regions, which second jog is located so near to one of the second and third shapes longitudinally that during lithographic printing, an inner corner of the second jog will round so as to extend at least partly into one of the channel regions. 
     
     
         13 . A lithographic mask set according to  claim 12 , wherein the mask set further includes shapes for connecting the second diffusion sub-region as a shared source of both the first and second transistors. 
     
     
         14 . A lithographic mask set according to  claim 10 , wherein the first shape further includes a second transversely extending jog on the second side of the first shape, the second jog having a third inner corner proximal to the second shape and a fourth inner corner proximal to the third shape,
 the third inner corner being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the third inner corner will round and extend at least partly into the first channel region,   and the fourth inner corner being located relative to the third shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the fourth inner corner will round and extend at least partly into the second channel region.   
     
     
         15 . An article of manufacture, comprising a computer readable storage medium, having stored thereon a computer readable definition of shapes for a photolithographic mask set for defining features to be formed on an integrated circuit using the mask set, wherein the features include a channel region for a transistor, a gate conductor overlying the channel region, and first and second diffusion regions on longitudinally opposite sides of the channel region, the first and second diffusion regions being of a first doping type and the channel region being of a second doping type opposite the first doping type, the first and second diffusion regions being connected in a circuit as respectively first and second current path terminals of the transistor,
 the shapes including a first shape for defining a geometric union of the channel region and the first and second diffusion regions, and a second shape for defining the gate conductor, the second shape crossing the first shape transversely, for use in a process in which the channel region is doped before the gate conductor is applied to the integrated circuit using the second shape, and the first and second diffusion regions are doped after the gate conductor is applied,   wherein the first shape has transversely opposite first and second sides along the length of the first diffusion region,   and wherein the first shape includes a first transversely extending jog on the first longitudinal side of the first shape, the first jog having an inner corner and an outer corner, the first jog being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, at least one of the inner and outer corners will round and extend at least partly within the channel region.   
     
     
         16 . An article of manufacture, comprising a computer readable storage medium, having stored thereon a computer readable definition of shapes for a photolithographic mask set for defining features to be formed on an integrated circuit using the mask set, wherein the features include first and second channel regions for respective first and second transistors, first and second gate conductors overlying respectively the first and second channel regions, first and second diffusion sub-regions on longitudinally opposite sides of the first channel region, and a third diffusion sub-region on the side of the second channel region longitudinally opposite the second diffusion sub-region, the first, second and third diffusion sub-regions being of a first doping type and the first and second channel regions being of a second doping type opposite the first doping type, the first and second diffusion sub-regions being connected in a circuit as respectively first and second current path terminals of the first transistor, and the second and third diffusion sub-regions being connected in a circuit as respectively first and second current path terminals of the second transistor, the shapes including a first shape for defining a geometric union of the first and second channel regions and the first, second and third diffusion sub-regions, a second shape for defining the first gate conductor and a third shape for defining the second gate conductor, the second and third shapes each crossing the first shape transversely, for use in a process in which the first and second channel regions are doped before the first and second gate conductors are applied to the integrated circuit using the second and third shapes, and the first, second and third diffusion sub-regions are doped after the first and second gate conductors are applied,
 wherein the first shape has transversely opposite first and second sides along the length of the second diffusion sub-region,   and wherein the first shape includes a transversely extending jog on the first side of the first shape, the jog having a first inner corner proximal to the second shape and a second inner corner proximal to the third shape,   the first inner corner of the jog being located relative to the second shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the first inner corner will round and extend at least partly within the first channel region,   and the second inner corner of the jog being located relative to the third shape longitudinally such that during lithographic printing of the first shape onto the integrated circuit, the second inner corner will round and extend at least partly within the second channel region.   
     
     
         17 . A method for revising a layout of a circuit design, for use in forming a lithographic mask set for use in fabricating an integrated circuit, the method being for use by a computer system having a processor and memory, the method comprising the steps of:
 the computer system identifying in a layout a subject transistor having shapes for defining on the integrated circuit source and drain diffusion regions and a gate conductor overlying a channel region, for which the source diffusion region is no wider than the drain diffusion region where they respectively meet the channel region, the layout including a first shape for defining at least the source diffusion region of the subject transistor, and a second shape for defining at least the gate conductor of the transistor; and   the computer system adding a transversely extending protrusion to the first shape, the protrusion having at least a portion which is on the same side of the gate conductor longitudinally as is the source diffusion region, the protrusion having an inner corner located relative to the gate conductor longitudinally such that during lithographic printing of the protrusion onto the integrated circuit, the corner will round and extend at least partly within the channel region.   
     
     
         18 . A method for revising a layout of a circuit design, for use in forming a lithographic mask set for use in fabricating an integrated circuit, the method being for use by a computer system having a processor and memory, the method comprising the steps of:
 the computer system identifying in a layout a subject transistor having shapes for defining on the integrated circuit source and drain diffusion regions and a gate conductor overlying a channel region, for which the source diffusion region is no wider than the drain diffusion region where they respectively meet the channel region, the layout including a first shape for defining at least the drain diffusion region of the subject transistor, and a second shape for defining at least the gate conductor of the transistor; and   the computer system adding a transversely intruding cut-out to the first shape, the cut-out having at least a portion which is on the same side of the gate conductor longitudinally as is the drain diffusion region, the cut-out having an outer corner located relative to the gate conductor longitudinally such that during lithographic printing of the cut-out onto the integrated circuit, the corner will round and extend at least partly within the channel region.   
     
     
         19 . An integrated circuit which includes a channel region for a transistor, a gate conductor overlying the channel region, and first and second diffusion regions on longitudinally opposite sides of the channel region, the first and second diffusion regions being of a first doping type and the channel region being of a second doping type opposite the first doping type, the first and second diffusion regions being connected in a circuit as respectively first and second current path terminals of the transistor,
 wherein the channel region has a first transverse width at a longitudinal position L 0  where the channel region meets the first diffusion region, a second transverse width at a longitudinal position L 2  where the channel region meets the second diffusion region, and a transverse width W 1  at a longitudinal position L 1  within the channel region, the width W 1  being less than both the first and second widths.   
     
     
         20 . An integrated circuit according to  claim 19 , wherein the channel region has transversely opposite first and second sides along the length of the channel region,
 and wherein both sides narrow toward each other from the longitudinal position L 0  to the longitudinal position L 1 .   
     
     
         21 . A method for laying out a circuit design, the circuit design specifying a transistor having source, drain and gate nodes, the method being for use on a computer system having a processor and a memory, comprising the steps of:
 the computer system laying out the circuit in a manner which defines first and second diffusion regions on longitudinally opposite sides of a gate conductor, the first diffusion region having a width larger than the second diffusion region; and   the computer system determining which of the diffusion regions has the larger width; and   the computer system, in dependence upon the determination made in the step of determining, laying out circuit interconnects in a manner which connects the diffusion region with the larger width as the source of the transistor.