Memory device, memory circuit and semiconductor integrated circuit having variable resistance

Abstract

A first variable resistor ( 5 ) is connected between a first terminal ( 7 ) and a third terminal ( 9 ) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal ( 7 ) and the third terminal ( 9 ). A second variable resistor ( 6 ) is connected between the third terminal ( 9 ) and a second terminal ( 8 ) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the third terminal ( 9 ) and the second terminal ( 8 ). Given pulse voltages are applied between the first terminal ( 7 ) and the third terminal ( 9 ) and between the third terminal ( 9 ) and the second terminal ( 8 ) to reversibly change the resistance values of the first and second variable resistors ( 5, 6 ), thereby recording one bit or multiple bits of information.

1 - 20 . (canceled) 
     
     
         21 . A memory circuit, comprising:
 a first memory block connected between a first node and a second node;   a first block-selecting transistor connected in series with the first memory block between the first node and the second node; and   a second memory block connected between an interconnect node and a third node, the interconnect node connecting the first memory block and the first block-selecting transistor to each other,   wherein each of the first and second memory blocks includes a plurality of memory cells connected in series, and   each of the plurality of memory cells includes
 a variable resistor connected between a first terminal and a second terminal and whose resistance value changes in response to a pulse voltage applied between the first terminal and the second terminal, and 
 a transistor connected in parallel with the variable resistor between the first terminal and the second terminal. 
   
     
     
         22 . The memory circuit of  claim 21 , wherein during writing of data, the first block-selecting transistor is turned ON,
 a transistor in a first memory cell of each of the plurality of the memory cells of the first memory block is turned OFF and a transistor in each memory cell other than the first memory cell of the plurality of memory cells in the first memory block is turned ON, and   a transistor in a second memory cell of each of the plurality of memory cells of the second memory block is turned OFF and a transistor in each memory cell other than the second memory cell of the plurality of memory cells in the second memory block is turned ON.   
     
     
         23 . The memory circuit according to  claim 22 , wherein during writing of data, a pulse voltage for increasing a resistance value of a variable resistor included in the first memory cell is applied between the first node and the second node, and a pulse voltage for reducing the resistance value of a variable resistor included in the second memory cell is applied between the first node and the third node. 
     
     
         24 . The memory circuit of  claim 21 , wherein during reading of data,
 the first block-selecting transistor is turned ON,   a transistor in a first memory cell of the plurality of the memory cells of the first memory block is turned OFF and a transistor in each memory cell other than the first memory cell of the plurality of memory cells in the first memory block is turned ON, and   a transistor in a second memory cell of the plurality of memory cells of the second memory block is turned OFF and a transistor included in each memory cell other than the second memory cell of the plurality of memory cells in the second memory block is turned ON.   
     
     
         25 . The memory circuit according to  claim 24 , wherein a voltage at the first node is detected with a given voltage applied between the second node and the third node. 
     
     
         26 . The memory circuit according to  claim 21 , wherein each of the plurality of memory cells are arranged in a matrix. 
     
     
         27 . A memory circuit, comprising:
 a first memory block connected between a first node and a second node;   a first block-selecting transistor connected in series with the first memory block between the first node and the second node;   a second memory block connected between the second node and a third node; and   a second block-selecting transistor connected in series with the second memory block between the second node and the third node,   wherein each of the first and second memory blocks includes a plurality of memory cells connected in series, and   each of the plurality of memory cells includes
 a variable resistor connected between a first terminal and a second terminal and whose resistance value changes in response to a pulse voltage applied between the first terminal and the second terminal, and 
 a transistor connected in parallel with the variable resistor between the first terminal and the second terminal. 
   
     
     
         28 . The memory circuit of  claim 27 , wherein during writing of data,
 the first block-selecting transistor and the second block-selecting transistor are turned ON,   a transistor in first a memory cell of the plurality of memory cells in the first memory block is turned OFF and a transistor in each memory cell other than the first memory cell of the plurality of memory cells in the first memory block is turned ON, and   a transistor in a second memory cell of the plurality of memory cells in the second memory block is turned OFF and a transistor in each memory cell other than the second memory cell of the plurality of memory cells in the second memory block is turned ON.   
     
     
         29 . The memory circuit of  claim 28 , wherein during writing of data, a pulse voltage for increasing the resistance value of a variable resistor included in the first memory cell is applied between the first node and the second node, and a pulse voltage for reducing the resistance value of a variable resistor included in the second memory cell is applied between the second node and the third node. 
     
     
         30 . The memory circuit of  claim 27 , wherein during reading of data,
 the first block-selecting transistor and the second block-selecting transistor are turned ON,   a transistor in a first memory cell of the plurality of memory cells in the first memory circuit is turned OFF and a transistor included in each memory cell other than the first memory cell of the plurality of memory cells in the first memory block is turned ON, and   a transistor in a second memory cell of the plurality of memory cells in the second memory circuit is turned OFF and a transistor in each memory cell of the plurality of memory cells other than the second memory cell is turned ON.   
     
     
         31 . The memory circuit of  claim 30 , wherein during reading of data, a voltage at the second node is detected with a given voltage applied between the first node and the third node. 
     
     
         32 - 36 . (canceled) 
     
     
         37 . A method for reading of data in a variable resistance memory cell having at least three terminals, comprising the steps of:
 applying a ground voltage to a first terminal of the at least three terminals;   applying a reproducing voltage that is lower that a recording voltage to a second terminal of the at least three terminals;   outputting a voltage from a third terminal of the at least three terminals.   
     
     
         38 . The method for reading of data according to  claim 37 , wherein the voltage output has multiple values corresponding to a number of voltage pulses applied in a recording operation. 
     
     
         39 . (canceled)