Defect pattern matching and verification in integrated circuit design and manufacturing

Abstract

A method is disclosed for correcting design defects in a circuit layout. The method includes storing first-level defect patterns in a first-level defect pattern library and identifying in a first circuit layout a first target that matches the shape of a first-level defect pattern in the first-level defect pattern library, and modifying the first target in the first circuit layout to produce a modified circuit layout. The method also includes storing second-level defect patterns in a second-level defect pattern library. The second-level defect patterns stored in the second-level defect pattern library are related to defects in circuit manufacturing. The first-level defect patterns are not stored in the second-level defect pattern library. A second target in the modified circuit layout is identified to increase manufacturing yield of the circuit layout. The second target substantially matches a second-level defect pattern in the second-level defect pattern library.

1 . A computer-assisted method for correcting design defects in a circuit layout, comprising:
 a first-level defect matching process comprising:
 storing first-level defect patterns in a first-level defect pattern library in a computer storage system; 
 using a computer processor to identify, in a first circuit layout, a first target that matches the shape of a first-level defect pattern in the first-level defect pattern library; and 
 modifying the first target in the first circuit layout to produce a modified circuit layout for verification by a second-level defect matching process; and 
   a second-level defect matching process, comprising:
 storing second-level defect patterns in a second-level defect pattern library in the computer storage system, wherein the second-level defect patterns in the second-level defect pattern library are related to defects in circuit manufacturing, wherein the first-level defect patterns are not stored in the second-level defect pattern library; and 
 identifying a second target in the modified circuit layout to increase manufacturing yield of the modified circuit layout, wherein the second target substantially matches a second-level defect pattern in the second-level defect pattern library. 
   
   
   
       2 . The computer-assisted method of  claim 1 , further comprising:
 setting a predetermined radius around the second target, wherein the step of identifying the second target in the modified circuit layout is conducted within the predetermined radius of the second target in the modified circuit layout.   
   
   
       3 . The computer-assisted method of  claim 1 , wherein the first-level defect pattern comprises a substantially polygon shape object. 
   
   
       4 . The computer-assisted method of  claim 1 , wherein the second-level defect pattern comprises a substantially polygon shape object. 
   
   
       5 . The computer-assisted method of  claim 4 , wherein the step of identifying a second target in the modified circuit layout comprises modeling the second target using one or more polygons. 
   
   
       6 . The computer-assisted method of  claim 1 , wherein at least one of the first-level defect patterns includes a defect target and neighboring circuit features surrounding the defect target, wherein the first target substantially matches the defect target pattern and the neighboring features surrounding the defect target pattern in the first-level defect pattern library. 
   
   
       7 . The computer-assisted method of  claim 1 , further comprising:
 storing second-level defect correction patterns each in association with one of the second-level defect patterns in the second-level defect pattern library, wherein the second-level defect correction patterns are configured to correct their respective second-level defect patterns; and   replacing the second target by the second-level defect correction pattern associated with the identified second-level defect pattern in the second-level defect pattern library.   
   
   
       8 . The computer-assisted method of  claim 7 , wherein the step of replacing the second target by the second-level defect correction pattern is after the step of modifying the first target in the modified circuit layout. 
   
   
       9 . The computer-assisted method of  claim 7 , wherein the second-level defect correction pattern applies optical proximity correction to the second target. 
   
   
       10 . The computer-assisted method of  claim 7 , wherein the second-level defect matching process further comprises:
 identifying the second target in a second circuit layout; and   replacing the second target in the second circuit layout by the second-level defect correction pattern associated with the identified second-level defect pattern in the second-level defect pattern library.   
   
   
       11 . The computer-assisted method of  claim 1 , further comprising:
 if a third target in the modified circuit layout does not match any of the second-level defect patterns in the second-level defect pattern library, developing a second-level defect correction pattern to replace the third target in the modified circuit layout.   
   
   
       12 . A computer-assisted method for correcting design defects in a circuit layout, comprising:
 a first-level defect matching process comprising:
 storing first-level defect patterns in a first-level defect pattern library in a computer storage system; 
 identifying using a computer processor, in a first circuit layout, a first target that matches the shape of a first-level defect pattern in the first-level defect pattern library; and 
 modifying the first target in the first circuit layout to produce modified circuit features for evaluation by a second-level defect matching process; and 
   a second-level defect matching process comprising:
 storing second-level defect patterns in a second-level defect pattern library in the computer storage system, wherein the second-level defect patterns in the second-level defect pattern library are obtained from two or more circuit layouts, wherein the second-level defect patterns stored in the second-level defect pattern library are not stored in the first-level defect pattern library wherein the first-level defect patterns are not stored in a second-level defect pattern library; and 
 identifying a second target in the modified circuit layout to increase the manufacturing yield of the modified circuit layout, wherein the second target substantially matches a second-level defect pattern in the second-level defect pattern library. 
   
   
   
       13 . The computer-assisted method of  claim 12 , further comprising:
 setting a predetermined radius around the second target, wherein the step of identifying the second target in the modified circuit layout is conducted within the predetermined radius of the second target in the modified circuit layout.   
   
   
       14 . The computer-assisted method of  claim 12 , wherein the first-level defect pattern comprises a substantially polygon shape object. 
   
   
       15 . The computer-assisted method of  claim 12 , wherein the second-level defect pattern comprises a substantially polygon shape object. 
   
   
       16 . The computer-assisted method of  claim 12 , wherein at least one of the first-level defect patterns includes a defect target and neighboring circuit features surrounding the defect target, wherein the first target substantially matches the defect target pattern and the neighboring features surrounding the defect target pattern in the first-level defect pattern library. 
   
   
       17 . The computer-assisted method of  claim 12 , further comprising:
 storing second-level defect correction patterns each in association with one of the second-level defect patterns in the second-level defect pattern library, wherein the second-level defect correction patterns are configured to correct their respective second-level defect patterns; and   replacing the second target by the second-level defect correction pattern associated with the identified second-level defect pattern in the second-level defect pattern library.   
   
   
       18 . The computer-assisted method of  claim 17 , wherein the step of replacing the second target by the second-level defect correction pattern is after the step of modifying the first target in the modified circuit layout. 
   
   
       19 . The computer-assisted method of  claim 17 , wherein the second-level defect correction pattern applies optical proximity correction to the second target. 
   
   
       20 . A computer-assisted method for correcting design defects in a circuit layout, comprising:
 a first-level defect matching process comprising:
 storing first-level defect patterns in a first-level defect pattern library in a computer storage system; 
 using a computer processor to identify, in a first circuit layout, a first target that matches the shape of a first-level defect pattern in the first-level defect pattern library; and 
 modifying the first target in the first circuit layout to produce modified circuit features for verification by a second-level defect matching process; and 
   a second-level defect matching process, comprising:
 storing second-level defect patterns in a second-level defect pattern library in the computer storage system, wherein the second-level defect patterns stored in the second-level defect pattern library are related to defects in circuit manufacturing, wherein the first-level defect patterns are not stored in the second-level defect pattern library; and 
 using a plurality of computer processors in communication with the computer storage system to identify a second target in the modified circuit layout to increase the manufacturing yield of the modified circuit layout, wherein the second target substantially matches a second-level defect pattern in the second-level defect pattern library.