Data memory device and controller with interface error detection and handling logic

Abstract

The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.

1 . A solid-state data memory device comprising:
 a semiconductor package;   a memory array provided in the semiconductor package;   an interface communicatively couplable to a device bus for receiving data to be stored to the memory array; and   an error detection component provided in the semiconductor package and associated with the interface of the solid-state data memory device, the error detection component configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.   
     
     
         2 . The solid-state data memory device of  claim 1 , wherein the semiconductor package comprises at least one semiconductor die provided within a housing, and wherein the memory array comprises multiple memory cells that can each store at least one bit. 
     
     
         3 . The solid-state data memory device of  claim 2 , wherein the memory array, interface, and error detection component are implemented on the same semiconductor die. 
     
     
         4 . The solid-state data memory device of  claim 2 , wherein the solid-state data memory device consists essentially of a flash memory chip. 
     
     
         5 . The solid-state data memory device of  claim 2 , wherein the semiconductor package comprises multiple input/output (I/O) signals for communicatively coupling the interface to the device bus, the multiple I/O signals enabling the data memory device to communicate with a controlling device for receiving input command, address, and data, and for transmitting output data. 
     
     
         6 . The solid-state data memory device of  claim 5 , wherein the semiconductor package comprises:
 a chip enable pin to enable the solid-state data memory device for operation;   a read enable pin to control reads to the I/O pins;   a write enable pin to control writes to the I/O pins;   a write protect pin to provide write and erase protection;   a ready/busy pin to indicate a status of the device as ready or busy;   a power supply pin; and   a ground pin.   
     
     
         7 . The solid-state data memory device of  claim 2 , wherein the housing of the semiconductor package has an overall size that is less than approximately 30 millimeters (mm) by 30 millimeters (mm). 
     
     
         8 . The solid-state data memory device of  claim 1 , wherein the error detection component comprises error detection logic that utilizes an error detection codeword appended to the data to determine if the data contains errors. 
     
     
         9 . The solid-state data memory device of  claim 8 , wherein the error detection logic calculates a second error detection codeword based on the data that is compared to the error detection codeword appended to the data to identify a number of errors in the data. 
     
     
         10 . The solid-state data memory device of  claim 8 , wherein the error detection logic utilizes redundancy code logic to analyze both the data and the error detection codeword appended to the data to identify a number of errors in the data. 
     
     
         11 . The solid-state data memory device of  claim 8 , wherein the data memory device is identified by a unique identifier that is stored in the data memory device, and wherein the error detection logic is initialized with the unique identifier prior to the error detection logic analyzing the data to identify errors. 
     
     
         12 . The solid-state data memory device of  claim 11 , wherein the error detection logic is configured to be initialized in response to a setup command received from a controlling device. 
     
     
         13 . A controller in a data storage system, the controller comprising:
 at least one interface for communicating data with a plurality of data memory devices;   a database containing a plurality of identifiers, wherein at least one identifier is associated with and uniquely identifies each of the plurality of data memory devices; and   a component configured to generate, for a transmission of data between the controller and a data memory device, an error control code based on the data and the at least one identifier associated with the data memory device.   
     
     
         14 . The controller of  claim 13 , wherein the plurality of data memory devices comprise a plurality of solid-state memory devices configured to communicate with the controller, each of the plurality of solid-state memory devices being uniquely identified by an identifier stored in the database. 
     
     
         15 . The controller of  claim 13 , wherein the error control code comprises one or more of an error detection code and an error correction code. 
     
     
         16 . The controller of  claim 13 , wherein the component is initialized with the at least one identifier prior to generating the error control code based on the data to be transmitted to the data memory device. 
     
     
         17 . The controller of  claim 13 , wherein the component generates the error control code by convoluting the at least one identifier associated with the data memory device with a cyclical redundancy code generated based on the data to be transmitted to the data memory device. 
     
     
         18 . The controller of  claim 13 , wherein the component comprises error detection logic that is initialized using the at least one identifier associated with the data memory device to detect errors in data received from the data memory device. 
     
     
         19 . The controller of  claim 18 , wherein the error detection logic receives a codeword appended to the data received from the data memory device, the codeword having been generated by the data memory device as a function of the at least one identifier associated with the data memory device. 
     
     
         20 . The controller of  claim 19 , wherein the error detection logic calculates a second codeword based on the data received from the data memory device and compares the second codeword to the codeword appended to the data to identify a number of errors in the data. 
     
     
         21 . A data storage system comprising:
 a plurality of data memory devices each comprising a memory element for storing data; and   a controller having at least one interface for communicating data with the plurality of data memory devices, wherein the controller is configured to provide data to be stored to a data memory device along a write path between an interface of the controller and the memory element of the data memory device; and   an error detection component associated with the data memory device and configured to detect errors on data transmitted between the controller and the data memory device, wherein the error detection component is provided in the write path and is configured to determine a number of errors in the data prior to the data being stored to the memory element of the data memory device.   
     
     
         22 . The data storage system of  claim 21 , wherein the data memory device comprises a solid-state data memory device having a data input communicatively coupled to the interface via a device bus, wherein the error detection component is provided between the data input and the memory element of the data storage device. 
     
     
         23 . The data storage system of  claim 22 , wherein data communicated between the controller and the solid-state data memory device includes an appended codeword that is generated based on a unique identifier for the solid-state memory device, and wherein the error detection component utilizes the appended codeword to determine if the data contains a number of errors. 
     
     
         24 . The data storage system of  claim 21 , wherein the plurality of data memory devices comprise a plurality of solid-state memory devices configured to communicate with the controller, each of the plurality of solid-state memory devices being uniquely identified by an identifier, and wherein each of the plurality of data memory devices comprises an error detection component configured to utilize the unique identifier of the data memory device to generate an error detection codeword for data transmitted over the between the data memory device and the controller. 
     
     
         25 . The data storage system of  claim 21 , wherein the data and commands associated with the data are transmitted to the data memory device over a common communication bus, wherein the error detection component is utilized to detect errors within the transmitted commands.