US2010177569A1PendingUtilityA1

Single poly eeprom allowing continuous adjustment of its threshold voltage

Assignee: TEXAS INSTRUMENTS INCPriority: Nov 8, 2007Filed: Mar 25, 2010Published: Jul 15, 2010
Est. expiryNov 8, 2027(~1.3 yrs left)· nominal 20-yr term from priority
G11C 2216/10G11C 16/0441H10B 41/60H10B 69/00H10B 41/30
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Claims

Abstract

A single-poly EEPROM memory device comprises a control gate isolated within a well of a first conductivity type in a semiconductor body of a second conductivity type, first and second tunneling regions isolated from one another within respective wells of the first conductivity type in the semiconductor body, a read transistor isolated within a well of the first conductivity type, and a floating gate overlying a portion of the control gate, the read transistor, and the first and second tunneling regions. The memory device is configured to be electrically programmed by changing a charge on the floating gate that changes the device threshold voltage. In one embodiment, the memory device is configured to be electrically programmed by applying a first potential between the first and second tunneling regions, and a second potential to the control gate, the second potential having a value less than the first potential.

Claims

exact text as granted — not AI-modified
1 . A method of electrically programming a memory device, comprising:
 providing the memory device comprising a floating gate overlying first and second tunneling regions, a control gate, and a read transistor;   applying a first potential to the first tunneling region;   applying a second potential to the second tunneling region; and   applying a third potential to the control gate to induce a charge on the floating gate thereby electrically programming a threshold voltage Vt of the memory device.   
   
   
       2 . The method of  claim 1 , wherein the first and second potentials are different, and wherein the third potential has a value which is between the first and second potentials. 
   
   
       3 . The method of  claim 1 , wherein the memory device comprises one of a single-poly EEPROM, and a modified OTP EPROM.

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