Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

1 . A semiconductor device comprising:
 a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film; and   a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, each of the memory cell gate structures including a first gate insulating film formed on the semiconductor substrate, a first gate electrode formed on the first gate insulating film, a second gate insulating film formed on the first gate electrode, and a second gate electrode formed on the second gate insulating film,   the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.   
   
   
       2 . The device according to  claim 1 , further comprising an interlayer insulating film formed between the select gate structures. 
   
   
       3 . The device according to  claim 2 , further comprising a contact plug formed in the interlayer insulating film. 
   
   
       4 . The device according to  claim 1 , wherein each of the select gate structures has another side which is opposite said opposed side, and said another side is substantially vertical to a major surface of the semiconductor substrate. 
   
   
       5 . The device according to  claim 1 , wherein the select gate structure is greater in width than the memory cell gate structure. 
   
   
       6 . The device according to  claim 1 , wherein a spacing between the select gate structure and the memory cell gate structure which are adjacent to each other is equal to a spacing between the memory cell gate structures which are adjacent to each other. 
   
   
       7 . The device according to  claim 1 , further comprising a first mask portion formed on each of the memory cell gate structures and a second mask portion formed on each of the select gate structures, the first and second mask portions being formed of the same material and being equal to each other in width. 
   
   
       8 . The device according to  claim 7 , further comprising a sidewall portion formed on the side of the second mask portion, the side of the sidewall portion being inclined. 
   
   
       9 . The device according to  claim 1 , wherein each of the select gate structures includes a first gate portion which is made of the same material as the first gate electrode and a second gate portion which is formed on the first gate portion and made of the same material as the second gate electrode, the first and second gate portions being in contact with each other. 
   
   
       10 . The device according to  claim 9 , wherein each of the select gate structures further includes an insulating portion which is formed between the first and second gate portions and made of the same material as the second insulating film. 
   
   
       11 . The device according to  claim 1 , wherein the semiconductor device has a NAND type memory structure including the select gate structures and the memory cell gate structures. 
   
   
       12 .- 20 . (canceled)