Buses for Pattern-Recognition Processors

Abstract

Disclosed are methods and systems, among which is a system that includes a pattern-recognition processor, a central processing unit (CPU) coupled to the pattern-recognition processor via a pattern-recognition bus, and memory coupled to the CPU via a memory bus. In some embodiments, the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.

1 . A system, comprising:
 a pattern-recognition processor;   a processing unit (PU) coupled to the pattern-recognition processor via a pattern-recognition bus; and   memory coupled to the PU via a memory bus, wherein the pattern-recognition bus and the memory bus form about the same number of connections to the pattern-recognition processor and the memory, respectively.   
     
     
         2 . The system of  claim 1 , wherein the pattern recognition bus forms at least one more connection than the memory bus. 
     
     
         3 . The system of  claim 2 , wherein the one more connection is an output interrupt signal. 
     
     
         4 . The system of  claim 1 , wherein each of a plurality of corresponding connections on the pattern-recognition bus and the memory bus serve a same respective function on both buses. 
     
     
         5 . The system of  claim 4 , wherein the plurality of corresponding connections that serve the same function on both buses include a chip enable signal and a clock signal. 
     
     
         6 . The system of  claim 4 , wherein the plurality of corresponding connections that serve the same function on both buses include a data strobe signal and a data mask signal. 
     
     
         7 . The system of  claim 1 , wherein the memory bus is a double data rate two memory bus. 
     
     
         8 . The system of  claim 1 , wherein a portion of the pattern-recognition bus serves at least one different function based on a mode of operation of the pattern-recognition processor. 
     
     
         9 . The system of  claim 8 , wherein the at least one different function includes address, command, and register select. 
     
     
         10 . The system of  claim 8 , wherein the at least one different function includes search criteria, output search results, and input data. 
     
     
         11 . The system of  claim 1 , wherein the pattern-recognition processor and PU are separate components. 
     
     
         12 . The system of  claim 1 , wherein the pattern-recognition processor is integrated into the same component as the PU. 
     
     
         13 . The system of  claim 10 , wherein the output search results comprise which of one or more search criteria was satisfied and which data from the input data satisfied the one or more search criteria. 
     
     
         14 . A method, comprising:
 transmitting a first type of signal on a portion of a pattern-recognition bus to a pattern-recognition processor;   changing a mode of the pattern-recognition processor; and   transmitting a second type of signal on the portion of the pattern-recognition bus.   
     
     
         15 . The method of  claim 14 , wherein transmitting the first type of signal comprises transmitting an address. 
     
     
         16 . The method of  claim 15 , wherein transmitting the second type of signal comprises transmitting either a command signal or a register select signal. 
     
     
         17 . The method of  claim 14 , wherein transmitting the first type of signal comprises transmitting a search criteria signal, and wherein changing the mode of the pattern-recognition processor comprises changing the mode of the pattern-recognition processor from a configuration mode. 
     
     
         18 . The method of  claim 17 , wherein transmitting the second type of signal comprises transmitting a data stream to be searched by the pattern-recognition processor, and wherein changing the mode of the pattern-recognition processor comprises changing the mode of the pattern-recognition processor to a search mode. 
     
     
         19 . The method of  claim 14 , wherein transmitting the first type of signal comprises transmitting a data stream to be searched by the pattern-recognition processor. 
     
     
         20 . The method of  claim 19 , wherein changing the mode of the pattern-recognition processor comprises changing the mode of the pattern-recognition processor to a search-report mode. 
     
     
         21 . The method of  claim 20 , wherein transmitting the second type of signal comprises transmitting a search results signal from the pattern-recognition processor. 
     
     
         22 . The method of  claim 20 , wherein changing the mode of the pattern-recognition processor to a search-report mode comprises:
 detecting that a data stream being searched has satisfied a search criterion;   transmitting an output interrupt signal to a PU; and   receiving a command to enter the search-report mode from the PU.   
     
     
         23 . The method of  claim 20 , wherein changing the mode of the pattern-recognition processor to a search report mode comprises:
 detecting that a data stream being searched has satisfied a search criterion;   storing a value that indicates whether the search criterion has been satisfied;   transmitting a signal indicative of the value to a PU; and   receiving a command to enter the search-report mode from the PU.   
     
     
         24 . The method of  claim 14 , comprising changing the mode of the pattern recognition processor in response to an event. 
     
     
         25 . The method of  claim 24 , wherein the event comprises satisfaction of a search criterion. 
     
     
         26 . A system, comprising:
 a pattern-recognition processor configured to interpret a first portion of signals received over a pattern-recognition bus the same way the first portion of signals are interpreted be a memory when received over a memory bus.   
     
     
         27 . The system of  claim 26 , wherein the pattern-recognition processor is configured to interpret a second portion of signals received over the pattern-recognition bus differently from the way the second portion of signals are interpreted by the memory when received over the memory bus. 
     
     
         28 . The system of  claim 26 , wherein the pattern-recognition processor is configured to interpret a third portion of signals received over the pattern-recognition bus both the same way as the third portion of signals are interpreted by the memory when received over the memory bus and differently from the way the third portion of signals are interpreted by the memory when received over the memory bus, depending on a mode of the pattern-recognition processor. 
     
     
         29 . The system of  claim 26 , comprising a CPU coupled to the pattern-recognition processor via the pattern-recognition bus. 
     
     
         30 . The system of  claim 29 , comprising a pattern-recognition bus controller coupled to the CPU via a control bus and a data bus and to the pattern-recognition processor via the pattern-recognition bus. 
     
     
         31 . The system of  claim 30 , comprising a memory bus controller coupled to the memory via the memory bus. 
     
     
         32 . The system of  claim 29 , wherein the pattern-recognition processor and the CPU are separate components. 
     
     
         33 . The system of  claim 29 , wherein the pattern-recognition processor and the CPU are integrated as a single component. 
     
     
         34 . The system of  claim 31 , wherein the memory bus controller and the pattern-recognition bus controller are separate components. 
     
     
         35 . The system of  claim 31 , wherein the memory bus controller and the pattern-recognition bus controller are integrated as a single component. 
     
     
         36 . The system of  claim 31 , wherein the pattern-recognition bus controller is configured to communicate with the pattern-recognition processor through a communication protocol that is at least similar to that used by the memory bus controller. 
     
     
         37 . The system of  claim 26 , wherein the pattern-recognition bus comprises about the same number of connections as the memory bus. 
     
     
         38 . The system of  claim 26 , wherein the pattern-recognition bus comprises about the same physical dimensions as the memory bus. 
     
     
         39 . A method, comprising:
 transmitting a plurality of different types of signals between a pattern-recognition processor and a processing unit on a portion of a pattern-recognition bus, wherein each of the plurality of different types of signals is associated with a different mode of the pattern-recognition processor.   
     
     
         40 . The method of  claim 39 , wherein the pattern-recognition processor is configured to interpret signals on the portion of the pattern-recognition bus differently in response to a change in the mode of the pattern-recognition processor. 
     
     
         41 . The method of  claim 39 , wherein the plurality of different types of signal comprise three different types of signals. 
     
     
         42 . The method of  claim 39 , wherein the plurality of different types of signals comprise an address signal, a control signal, a status signal, or a combination thereof. 
     
     
         43 . The method of  claim 42 , wherein the plurality of different types of signals comprise register select signal. 
     
     
         44 . The method of  claim 39 , wherein transmitting the plurality of different types of signals comprises transmitting a data stream to be searched by the pattern-recognition processor to the pattern-recognition processor when in a search mode and transmitting a search results signal from the pattern-recognition processor when in a reporting mode.