Semiconductor device manufacturing method and semiconductor integrated circuit device

Abstract

A semiconductor device manufacturing method includes forming a first insulating film on a semiconductor substrate, forming a first conductor film on the first insulating film, forming a second insulating film on the first conductor film, forming a first line-and-space pattern by etching the second insulating film and the first conductor film, forming a etched region etched into a second line-and-space pattern perpendicular to the first line-and-space pattern by etching the second insulating film, the first conductor film, the first insulating film, and the semiconductor substrate, burying a third insulating film in the etched region, removing the second insulating film, forming a fourth insulating film on the first conductor film and the third insulating film, forming a second conductor film on the fourth insulating film, and forming a third line-and-space pattern parallel to the first line-and-space pattern by etching the second conductor film.

1 .- 5 . (canceled) 
   
   
       6 . A semiconductor integrated circuit device comprising:
 a semiconductor substrate having an element isolation region extending in a first direction, and an element region defined by the element isolation region;   a gate insulating film formed on the element region;   a charge storage layer formed on the gate insulating film, and having a first side surface and a second side surface along the first direction and a third side surface and a fourth side surface along a second direction perpendicular to the first direction, the first side surface being in contact with the element isolation region;   a first insulating film formed above the element region, and in contact with the third side surface of the charge storage layer;   a second insulating film formed above the element region, and in contact with the fourth side surface of the charge storage layer;   an inter-gate insulating film formed on the first insulating film, the second insulating film, the charge storage layer, and the element isolation region; and   a control gate formed on the inter-gate insulating film, opposing the charge storage layer via the inter-gate insulating film, and extending in the second direction.   
   
   
       7 . The device according to  claim 6 , wherein a position of an upper surface of the charge storage layer is lower than a position of an upper surface of the first insulating film and the second insulating film, and a position of an upper surface of the element isolation region. 
   
   
       8 . The device according to  claim 6 , wherein a position of an upper surface of the charge storage layer is higher than a position of an upper surface of the first insulating film and the second insulating film, and a position of an upper surface of the element isolation region. 
   
   
       9 . The device according to  claim 6 , wherein a position of an upper surface of the charge storage layer is lower than a position of an upper surface of the first insulating film and the second insulating film, and higher than a position of an upper surface of the element isolation region below the control gate. 
   
   
       10 . The device according to  claim 9 , wherein a position of an upper surface of the inter-gate insulating film on the first insulating film, the second insulating film, and the element isolation region is the same as a position of an upper surface of the control gate. 
   
   
       11 . The device according to  claim 10 , further comprising:
 an interlayer dielectric film formed on the control gate and the inter-gate insulating film, having a contact hole which exposes the upper surface of the control gate and the upper surface of the inter-gate insulating film, and made of an insulator different from the inter-gate insulating film; and   a conductive contact formed in the contact hole and electrically connected to the control gate.   
   
   
       12 . The device according to  claim 11 , which further comprises an address decoding circuit, and
 in which the conductive contact connects an output of the address decoding circuit and the control gate.   
   
   
       13 . The device according to  claim 8 , wherein a length in the first direction of the charge storage layer is smaller than a length in the first direction of the control gate. 
   
   
       14 . The device according to  claim 8 , wherein letting L CG  be a length in the first direction of the control gate, t IGI  be a thickness of the inter-gate insulating film on the third side surface and the fourth side surface along the second direction of the charge storage layer, and M A  be an alignment margin in the first direction when processing the control gate, a length L FG  in the first direction of the charge storage layer has a relationship indicated by L FG <L CG −2M A −2t IGI . 
   
   
       15 . The device according to  claim 13 , wherein the control gate opposes the upper surface, the first side surface, the second side surface, the third side surface, and the fourth side surface of the charge storage layer via the inter-gate insulating film. 
   
   
       16 . The device according to  claim 13 , wherein source/drain diffusion layers are formed in the element region below the first insulating film and the second insulating film and have a conductivity type opposite to a conductivity type of the semiconductor substrate, and a lower surface of the control gate opposes the source/drain diffusion layers via at least the first insulating film, the second insulating film, and the inter-gate insulating film. 
   
   
       17 . The device according to  claim 16 , wherein when suppressing charge injection to the charge storage layer, a channel produced in the element region below the charge storage layer is electrically floated, a potential of the channel is capacitive coupled with a potential of the control gate. 
   
   
       18 . The device according to  claim 6 , wherein the control gate is made of a material selected from the group consisting of cobalt, nickel, titanium, cobalt silicide, nickel silicide, titanium silicide, tungsten, aluminum, and copper. 
   
   
       19 . The device according to  claim 6 , wherein the semiconductor integrated circuit device is a NAND flash memory. 
   
   
       20 . The device according to  claim 6 , wherein the semiconductor integrated circuit device is a multilevel nonvolatile semiconductor memory.