Chip packages with power management integrated circuits and related techniques

Abstract

Chip packages having power management integrated circuits are described. Power management integrated circuits can be combined with on-chip passive devices, and can provide voltage regulation, voltage conversion, dynamic voltage scaling, and battery management or charging. The on-chip passive devices can include inductors, capacitors, or resistors. Power management using a built-in voltage regulator or converter can provide for immediate adjustment of the voltage range to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices. Related fabrication techniques are described.

1 . A chip package comprising:
 a substrate:   a first chip over the substrate;   a second chip over the substrate; and   a voltage regulator device over the substrate, wherein the voltage regulator device is configured and arranged to accommodate different voltage needs of the first chip and second chip.   
     
     
         2 . The chip package of  claim 1 , wherein the voltage regulator device comprises a semiconductor chip, wherein the semiconductor chip includes:
 a silicon substrate;   multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;   a first dielectric layer over the silicon substrate;   a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;   a second dielectric layer between the first and second metal layers;   a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and   an inductor component and a capacitor component connected to the pads through a first solder layer, wherein the inductor component, the capacitor component, the switch controller and the voltage feedback device form the voltage regulator.   
     
     
         3 . The chip package of  claim 2 , wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers. 
     
     
         4 . The chip package of  claim 2 , further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure. 
     
     
         5 . The chip package of  claim 4 , wherein the under bump metal structure comprises a nickel layer. 
     
     
         6 . The chip package of  claim 4 , wherein the under bump metal structure comprises a copper layer. 
     
     
         7 . The chip package of  claim 1 , wherein the second chip is over the first chip. 
     
     
         8 . The chip package of  claim 1 , wherein the substrate comprises a Ball Grid Array (BGA) substrate. 
     
     
         9 . A chip package comprising:
 a substrate:   a first chip over the substrate;   a second chip over the substrate; and   a voltage converter device over the substrate, wherein the voltage regulator device is configured and arranged to accommodate different voltage needs of the first chip and second chip.   
     
     
         10 . The chip package of  claim 9 , wherein the voltage converter device comprises a semiconductor chip, wherein the semiconductor chip includes:
 a silicon substrate;   multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;   a first dielectric layer over the silicon substrate;   a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;   a second dielectric layer between the first and second metal layers;   a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and   an inductor component and a capacitor component connected to the pads through a first solder layer, wherein the inductor component, the capacitor component, the switch controller and the voltage feedback device form an on-chip voltage converter.   
     
     
         11 . The chip package of  claim 10 , wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers. 
     
     
         12 . The chip package of  claim 10 , further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure. 
     
     
         13 . The chip package of  claim 12 , wherein the under bump metal structure comprises a nickel layer. 
     
     
         14 . The chip package of  claim 12 , wherein the under bump metal structure comprises a copper layer. 
     
     
         15 . The chip package of  claim 9 , wherein the second chip is over the first chip. 
     
     
         16 . The chip package of  claim 9 , wherein the substrate comprises a ball grid array (BGA) substrate. 
     
     
         17 . A chip package comprising:
 a substrate:   a first chip over the substrate;   a second chip over the substrate; and   a power management device over the substrate, wherein the power management device is configured and arranged to accommodate different voltage needs of the first chip and the second chip.   
     
     
         18 . The chip package of  claim 17 , wherein the power management device comprises a semiconductor chip, wherein the semiconductor chip includes:
 a silicon substrate;   multiple active devices in or over the silicon substrate, wherein the active devices comprise a switch controller and a voltage feedback device, wherein the switch controller and the voltage feedback device comprise a plurality of MOS devices;   a first dielectric layer over the silicon substrate;   a metallization structure over the first dielectric layer, wherein the metallization structure is connected to the active devices, and wherein the metallization structure comprises a first metal layer and a second metal layer over the first metal layer;   a second dielectric layer between the first and second metal layers;   a passivation layer over the metallization structure and over the first and second dielectric layers, an opening in the passivation layer exposing a pad and a contact pad of the metallization structure; and   an inductor component and a capacitor component connected to the pads through a first solder layer.   
     
     
         19 . The chip package of  claim 18 , wherein the passivation layer comprises a silicon nitride layer having a thickness of more than 0.3 micrometers. 
     
     
         20 . The chip package of  claim 18 , further comprising an under bump metal structure between the pad and the inductor component and the capacitor component, wherein the first solder layer is over the under bump metal structure. 
     
     
         21 . The chip package of  claim 20 , wherein the under bump metal structure comprises a nickel layer. 
     
     
         22 . The chip package of  claim 20 , wherein the under bump metal structure comprises a copper layer. 
     
     
         23 . The chip package of  claim 17 , wherein the second chip is over the first chip. 
     
     
         24 . The chip package of  claim 17 , wherein the substrate comprises a Ball Grid Array (BGA) substrate.