Non-Conductive Planarization of Substrate Surface for Mold Cap

Abstract

Consistent with an example embodiment, there is a method for fabricating a semiconductor package having a substrate. The method comprises defining an encapsulation boundary on a surface of the substrate; the encapsulation boundary is divided into a molding region and a non-molding region. Over the substrate, a plurality of conductive traces is provided. Each conductive trace has an inner connection located in the molding region and an outer connection located in the non-molding region. A plurality of non-conducting dummy traces across the encapsulation boundary is provided. The plurality of non-conductive dummy traces are interposed among the conductive traces and are spaced apart at an interval less than a predetermined minimum air-vein forming distance (Dmln). A solder mask over the substrate covers the conductive traces and the non-conductive dummy traces. The molding region of the substrate is encapsulated with a molding compound.

1 . A method for fabricating a semiconductor package having a substrate, the method comprising:
 defining an encapsulation boundary on a surface of the substrate, the encapsulation boundary divided into a molding region and a non-molding region;   providing a plurality of conductive traces over the substrate, each conductive trace having an inner connection located in the molding region and an outer connection located in the non-molding region;   providing a plurality of non-conducting dummy traces across the encapsulation boundary, the plurality of dummy traces interposed among the conductive traces that are spaced apart at an interval greater than a predetermined minimum air-vein forming distance;   providing a solder mask over the substrate covering the conductive traces and the non-conductive dummy traces; and   encapsulating the molding region of substrate with a molding compound.   
     
     
         2 . The method as recited in  claim 1 , wherein the predetermined minimum air-vein forming distance is less than about 0.9 mm. 
     
     
         3 . The method as recited in  claim 1 , wherein the predetermined minimum air-vein form distance is less than about 0.5 mm. 
     
     
         4 . A packaging substrate having a substantially planar surface, the substrate comprising:
 a laminate material having a top metal layer of conductive traces of a predetermined vertical thickness, the conductive traces in a predetermined arrangement having dense regions and sparse regions of conductive traces, the sparse regions of adjacent conductive traces spaced apart a an interval greater than a predetermined minimum air-vein forming distance;   a non-conducting material interspersed as dummy traces between the sparse regions of conductive traces, the dummy traces having a thickness comparable to the vertical thickness of the conductive traces, the dummy traces providing a planar surface and reducing spacing between features to an interval less than the predetermined minimum air-vein forming distance; and   a solder mask applied over the substrate to cover the top metal layer and non-conducting material.   
     
     
         5 . The IC substrate as recited in  claim 4 , wherein the solder mask is the same material as the non-conducting material. 
     
     
         6 . An integrated circuit device device comprising:
 an IC die mounted in a die attach area in a laminate substrate, the laminate substrate having a surface divided into a area inside an encapsulation boundary region and an area outside the encapsulation boundary region, the die attach area within the area inside the encapsulation boundary, the IC die encapsulated with a molding compound within the encapsulation boundary region;   the laminate material having a top metal layer of conductive traces of a predetermined vertical thickness, the conductive traces in a predetermined arrangement having dense regions and sparse regions of conductive traces, the sparse regions of adjacent conductive traces spaced apart at an interval greater than a predetermined minimum air-vein forming distance, each conductive trace having an inner connection located inside the encapsulation boundary and an outer connection located outside the encapsulation boundary region, the inner connection of each conductive trace connecting the IC die at predefined pads; and   a non-conducting material interspersed as dummy traces between the sparse regions of conductive traces across the encapsulation boundary region, the dummy traces having a thickness comparable to the vertical thickness of the conductive traces, the dummy traces providing a planar surface and reducing spacing between features to an interval less than the predetermined minimum air-vein forming distance.   
     
     
         7 . The IC device as recited in  claim 6 , wherein a solder mask is deposited on the surface of the laminate substrate.