Semiconductor device having a stacked chip structure

Abstract

A semiconductor device is formed by mutually connecting a first semiconductor chip with second and third semiconductor chips arranged side by side, with the active surface of the first chip faced to those of the second and third chip. Both the second and third semiconductor chips have functional elements on their active surfaces. The first semiconductor chip has, in its active surface, a wiring for connecting the second semiconductor chip and the third semiconductor chip, and a terminal for external connection on its surface opposite to its active surface.

1 . A device comprising:
 a substrate having a substrate active surface;   a first chip connected to the substrate;   a first wiring formed in the substrate and arranged to connect the substrate to the first chip;   a second wiring formed in the first chip;   a substrate through-hole penetrating through the substrate in a thickness direction of the substrate;   a first through-hole penetrating through the first chip in a thickness direction of the first chip; and   a first bump bonding the substrate through-hole and the first through-hole, wherein   the first wiring is greater in sectional area than the second wiring.   
   
   
       2 . The device according to  claim 1 , wherein the bump is arranged beneath the first through-hole. 
   
   
       3 . The device according to  claim 1 , wherein conductors are arranged in the substrate through-hole and the first through-hole, respectively. 
   
   
       4 . The device according to  claim 1 , further comprising a second chip connected to the first chip. 
   
   
       5 . The device according to  claim 4 , further comprising a second bump arranged to connect the second chip to the first chip. 
   
   
       6 . The device according to  claim 5 , wherein the second chip has a second through-hole penetrating the second chip in a thickness direction of the second chip. 
   
   
       7 . The device according to  claim 6 , further comprising a third chip connected to the second chip. 
   
   
       8 . The device according to  claim 7 , further comprising a third bump arranged to connect the third chip to the second chip. 
   
   
       9 . The device according to  claim 7 , wherein a plurality of the second chips are stacked on one another. 
   
   
       10 . The device according to  claim 7 , wherein the third chip has no through-hole. 
   
   
       11 . A device comprising:
 a substrate having a substrate active surface;   a first chip connected to the substrate;   a first wiring formed in the substrate and arranged to connect the substrate to the first chip;   a second wiring formed in the first chip;   a substrate through-hole penetrating through the substrate in a thickness direction of the substrate;   a first through-hole penetrating through the first chip in a thickness direction of the first chip; and   a first bump bonding the substrate through-hole and the first through-hole, wherein the first wiring is greater in width and thickness than the second wiring, or same in thickness and greater in width as compared to the second wiring, or same in width and greater in thickness as compared to the second wiring.   
   
   
       12 . The device according to  claim 11 , wherein the bump is arranged beneath the first through-hole. 
   
   
       13 . The device according to  claim 11 , wherein conductors are arranged in the substrate through-hole and the first through-hole, respectively. 
   
   
       14 . The device according to  claim 11 , further comprising a second chip connected to the first chip. 
   
   
       15 . The device according to  claim 14 , further comprising a second bump arranged to connect the second chip to the first chip. 
   
   
       16 . The device according to  claim 15 , wherein the second chip has a second through-hole penetrating the second chip in a thickness direction of the second chip. 
   
   
       17 . The device according to  claim 16 , further comprising a third chip connected to the second chip. 
   
   
       18 . The device according to  claim 17 , further comprising a third bump arranged to connect the third chip to the second chip. 
   
   
       19 . The device according to  claim 17 , wherein a plurality of the second chips are stacked on one another. 
   
   
       20 . The device according to  claim 17 , wherein the third chip has no through-hole.