Method for active pinch off of an ovonic unified memory element

Abstract

A method of manufacturing a phase change memory (PCM) includes forming a pinch plate layer transversely to a PCM layer that is insulated from the pinch plate layer by a dielectric layer. Biasing the pinch plate layer causes a depletion region to form in the PCM layer. During a read of the PCM in a reset or partial reset state the depletion region increases the resistance of the PCM layer significantly.

1 . A method, comprising:
 forming a first phase change memory cell, the forming including:
 forming a first phase change layer; 
 forming first and second electrodes at opposite first and second ends of the first phase change layer; and 
 forming a first dielectric layer on a side of the first phase change layer; and 
   forming a conductive layer separated from the first phase change layer by the first dielectric layer, the conductive layer being configured to produce a carrier depletion region in the first phase change layer.   
   
   
       2 . The method of  claim 1 , further comprising forming the depletion region by biasing the conductive layer. 
   
   
       3 . The method of  claim 1  wherein forming the first phase change memory cell includes:
 forming a second dielectric layer surrounding the first electrode, wherein forming the conductive layer includes forming the conductive layer on the second dielectric layer;   forming a third dielectric layer on the conductive layer; and   forming a first pore that extends in the second and third dielectric layers, wherein the first dielectric layer is a spacer layer that lines a wall of the first pore and the first phase change layer is positioned in the pore.   
   
   
       4 . The method of  claim 3  wherein:
 forming the first pore includes forming the first pore through the conductive layer;   the first dielectric layer lines opposite sides of the first pore; and   the conductive layer completely laterally surrounds mid-portions of the first phase change layer and the first dielectric layer.   
   
   
       5 . The method of  claim 4 , further comprising:
 forming a second phase change memory cell, the forming including:
 forming a third electrode in the second dielectric layer, the third electrode being spaced apart from the first electrode of the first phase change memory cell; 
 forming a second pore in the second and third dielectric layers, through the conductive layer, and on the third electrode; 
 lining a sidewall of the second pore with a dielectric spacer; and 
 forming a second phase change layer in the second pore and surrounded by the dielectric spacer, wherein forming the conductive layer includes forming the conductive layer immediately adjacent to the dielectric spacer, the conductive layer being configured to produce a carrier depletion region in the second phase change layer. 
   
   
   
       6 . The method of  claim 1 , further comprising forming a second dielectric layer, the first and second electrodes being formed in the second dielectric layer and being spaced apart from one another; wherein:
 forming the first phase change layer includes forming the first phase change layer on, and extending between, the first and second electrodes;   forming the first dielectric layer includes forming the first dielectric layer on the first phase change layer; and   forming the conductive layer includes forming the conductive layer on the first dielectric layer.   
   
   
       7 . The method of  claim 6  wherein:
 forming the first phase change memory cell includes forming a recess positioned over the first and second electrodes and extending between the first and second electrodes; and   forming the first phase change layer includes depositing the first phase change layer in the recess.   
   
   
       8 . A phase change memory comprising:
 a first phase change memory cell that includes:
 a first phase change layer; 
 first and second electrodes at opposite first and second ends of the first phase change layer; 
 a first dielectric layer on a side of the first phase change layer; and 
   a conductive layer separated from the first phase change layer by the first dielectric layer, the conductive layer being configured to produce a carrier depletion region in the first phase change layer.   
   
   
       9 . The phase change memory of  claim 8  wherein the depletion region in the first phase change layer forms by biasing the conductive layer. 
   
   
       10 . The phase change memory of  claim 8  wherein the first phase change memory cell further comprises:
 a second dielectric layer surrounding the first electrode, wherein the conductive layer forms on the second dielectric layer;   a third dielectric layer on the conductive layer; and   a first pore that extends into the second and third dielectric layers, wherein the first dielectric layer is a spacer layer that lines a wall of the first pore and the first phase change layer is positioned in the pore.   
   
   
       11 . The phase change memory of  claim 10  wherein the first pore is formed through the conductive layer, the first dielectric layer lines opposite sides of the first pore, and the conductive layer completely laterally surrounds mid-portions of the first phase change layer and the first dielectric layer. 
   
   
       12 . The phase change memory of  claim 11 , further comprising:
 a second phase change memory cell that includes:
 a third electrode in the second dielectric layer, the third electrode begins spaced apart from the first electrode of the first phase change memory cell; 
 a second pore in the second and third dielectric layers, through the conductive layer, and on the third electrode; 
 a dielectric spacer lining a sidewall of the second pore; and 
 a second phase change layer in the second pore surrounded by the dielectric spacer, wherein the conductive layer is immediately adjacent to the dielectric spacer, the conductive layer is configured to produce a carrier depletion region in the second phase change layer. 
   
   
   
       13 . The phase change memory of  claim 8 , further comprising:
 a second dielectric layer, the first and second electrodes formed in the second dielectric layer and spaced apart from one another, wherein:   the first phase change layer forms on, and extending between, the first and second electrodes;   the first dielectric layer forms on the first phase change layer; and   the conductive layer forms on the first dielectric layer.   
   
   
       14 . The phase change memory of  claim 13  wherein:
 the first phase change memory cell includes a recess positioned over the first and second electrodes and extending between the first and second electrodes; and   the first phase change layer is deposited in the recess.   
   
   
       15 . A system, comprising:
 a processor; and   a phase change memory including:
 a first phase change memory cell that includes:
 a first phase change layer; 
 first and second electrodes at opposite first and second ends of the first phase change layer; 
 a first dielectric layer on a side of the first phase change layer; and 
 
 a conductive layer separated from the first phase change layer by the first dielectric layer, the conductive layer being configured to produce a carrier depletion region in the first phase change layer. 
   
   
   
       16 . The system of  claim 15  wherein the depletion region in the first phase change layer forms by biasing the conductive layer. 
   
   
       17 . The system of  claim 15  wherein the first phase change memory cell further comprises:
 a second dielectric layer surrounding the first electrode, wherein the conductive layer forms on the second dielectric layer;   a third dielectric layer on the conductive layer; and   a first pore that extends into the second and third dielectric layers, wherein the first dielectric layer is a spacer layer that lines a wall of the first pore and the first phase change layer is positioned in the pore.   
   
   
       18 . The system of  claim 17  wherein the first pore is formed through the conductive layer, the first dielectric layer lines opposite sides of the first pore, and the conductive layer completely laterally surrounds mid-portions of the first phase change layer and the first dielectric layer. 
   
   
       19 . The system of  claim 18 , further comprising:
 a second phase change memory cell that includes:
 a third electrode in the second dielectric layer, the third electrode begins spaced apart from the first electrode of the first phase change memory cell; 
 a second pore in the second and third dielectric layers, through the conductive layer, and on the third electrode; 
 a dielectric spacer lining a sidewall of the second pore; and 
 a second phase change layer in the second pore surrounded by the dielectric spacer, wherein the conductive layer is immediately adjacent to the dielectric spacer, the conductive layer is configured to produce a carrier depletion region in the second phase change layer. 
   
   
   
       20 . The system of  claim 15 , further comprising:
 a second dielectric layer, the first and second electrodes formed in the second dielectric layer and spaced apart from one another, wherein:   the first phase change layer forms on, and extending between, the first and second electrodes;   the first dielectric layer forms on the first phase change layer; and   the conductive layer forms on the first dielectric layer.   
   
   
       21 . The system of  claim 20  wherein:
 the first phase change memory cell includes a recess positioned over the first and second electrodes and extending between the first and second electrodes; and   the first phase change layer is deposited in the recess.