Memory system

Abstract

A memory system ( 10 ) is disclosed, which comprises a flash-EEPROM nonvolatile memory ( 11 ) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory ( 13 ) that temporarily stores data of the flash-EEPROM nonvolatile memory ( 11 ), a control circuit ( 12, 14 ) that controls the flash-EEPROM nonvolatile memory ( 11 ) and the cache memory ( 13 ), and an interface circuit ( 16 ) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.

1 . A memory system comprising a flash-EEPROM nonvolatile memory having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory that temporarily stores data of the flash-EEPROM nonvolatile memory, a control circuit that controls the flash-EEPROM nonvolatile memory and the cache memory, and an interface circuit that communicates with a host, in which
 the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.   
     
     
         2 . The memory system according to  claim 1 , wherein the control circuit further has a function of using an identification number added to data to be written into the flash-EEPROM memory as the determination condition. 
     
     
         3 . The memory system according to  claim 1 , wherein the control circuit has a function of transferring read data from the target area to the cache memory. 
     
     
         4 . The memory system according to  claim 1 , wherein the control circuit has a function of variably changing the preset criterion count number of data “0”. 
     
     
         5 . The memory system according to  claim 4 , wherein the control circuit further has a function of using an identification number added to data to be written into the flash-EEPROM memory as the determination condition. 
     
     
         6 . The memory system according to  claim 4 , wherein the control circuit includes a setting register functioning as means for variably changing the criterion count number of data “0”, and a “0” data count module that counts the count number of data “0” of the read data and functions to compare the criterion count number set by the setting register with the count number of data “0” counted by the “0” data count module to detect an erased area and determine the written area/unwritten area. 
     
     
         7 . The memory system according to  claim 1 , wherein the target area is an individual memory block of the flash-EEPROM nonvolatile memory and the control circuit reads data for each unit area of the memory block that is the target area, determines whether the unit area from which data is read is an erased area according to the determination condition to determine a written area/unwritten area. 
     
     
         8 . The memory system according to  claim 7 , wherein one unit of the memory block is a page unit and the data is read in an ascending order of page addresses from individual pages of one memory block. 
     
     
         9 . The memory system according to  claim 8 , wherein the control circuit determines whether a page from which data is read is an erased page according to the determination condition to determine a written area/unwritten area while transferring data read from the individual pages to the cache memory. 
     
     
         10 . The memory system according to  claim 9 , wherein the control circuit interrupts transfer of read data to the cache memory and reading of data from the flash-EEPROM nonvolatile memory when it is determined that the page of the read data is an erased area. 
     
     
         11 . The memory system according to  claim 10 , wherein the control circuit further has a function of using a successive number of erased pages as the determination condition. 
     
     
         12 . The memory system according to  claim 10 , wherein the control circuit further has a function of using an identification number added to data to be written into the flash-EEPROM memory as the determination condition. 
     
     
         13 . The memory system according to  claim 1 , wherein the control circuit further has a function of using an error correction result based on an ECC system with respect to write data of the flash-EEPROM nonvolatile memory as the determination condition. 
     
     
         14 . The memory system according to  claim 13 , wherein the control circuit further has a function of using an identification number added to data to be written into the flash-EEPROM memory as the determination condition.