US2010156450A1PendingUtilityA1

Enabling higher operation speed and/or lower power consumption in a semiconductor integrated circuit device

Assignee: PANASONIC CORPPriority: Oct 12, 2006Filed: Feb 23, 2010Published: Jun 24, 2010
Est. expiryOct 12, 2026(~0.2 yrs left)· nominal 20-yr term from priority
H03K 19/00384
43
PatentIndex Score
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Cited by
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Claims

Abstract

A semiconductor integrated circuit device 100 A includes: an integrated circuit body 106 A having a plurality of MOSFETs on a semiconductor substrate; a plurality of elements 102 A to be measured placed on the same substrate as the plurality of MOSFETs; a monitor circuit 105 A for selecting an element to be measured whose measured parameter value is in a predetermined rank among the plurality of elements 102 A to be measured as an element 101 A to be measured for monitoring; and an operation parameter adjustment circuit 107 for adjusting an operation parameter 108 supplied to the integrated circuit body 106 A based on the measured parameter 104 A of the element to be measured for monitoring.

Claims

exact text as granted — not AI-modified
1 - 17 . (canceled) 
   
   
       18 . A semiconductor integrated circuit device comprising:
 an integrated circuit body having a plurality of MOSFETs on a semiconductor substrate;   a plurality of elements to be measured placed on the same substrate as the plurality of MOSFETs;   a comparator for performing magnitude comparison of measured parameters of the plurality of elements to be measured;   a monitor circuit for determining an order of magnitude of the measured parameters of the plurality of elements to be measured based on a result of the magnitude comparison of the comparator, and selecting an element to be measured for monitoring from the plurality of elements to be measured based on the determined order; and   an operation parameter adjustment circuit for adjusting an operation parameter supplied to the integrated circuit body based on the measured parameter of the element to be measured for monitoring,   wherein each of the plurality of elements to be measured is a chain of a plurality of inverter circuits connected in series, and   the measured parameter is a delay time in the chain.   
   
   
       19 . A semiconductor integrated circuit device comprising:
 an integrated circuit body having a plurality of MOSFETs on a semiconductor substrate;   a plurality of elements to be measured placed on the same substrate as the plurality of MOSFETs;   a comparator for performing magnitude comparison of measured parameters of the plurality of elements to be measured;   a monitor circuit for determining an order of magnitude of the measured parameters of the plurality of elements to be measured based on a result of the magnitude comparison of the comparator, and selecting an element to be measured for monitoring from the plurality of elements to be measured based on the determined order; and   an operation parameter adjustment circuit for adjusting an operation parameter supplied to the integrated circuit body based on the measured parameter of the element to be measured for monitoring,   wherein the monitor circuit selects an element to be measured whose measured parameter value is any one of the maximum, the minimum and the median from the plurality of elements to be measured as the element to be measured for monitoring, and   the operation parameter adjustment circuit adjusts at least one operation parameter among the operation frequency, the power supply voltage and the substrate voltage supplied to the integrated circuit body,   each of the plurality of elements to be measured is a chain of a plurality of inverter circuits connected in series, and   the measured parameter is a delay time in the chain.   
   
   
       20 . The device of  claim 18 , wherein the monitor circuit is a circuit in which outputs of the plurality of chains are connected with an AND circuit. 
   
   
       21 . The device of  claim 19 , wherein the monitor circuit is a circuit in which outputs of the plurality of chains are connected with an AND circuit. 
   
   
       22 . The device of  claim 18 , wherein the monitor circuit is a circuit in which outputs of the plurality of chains are connected with an OR circuit. 
   
   
       23 . The device of  claim 19 , wherein the monitor circuit is a circuit in which outputs of the plurality of chains are connected with an OR circuit. 
   
   
       24 . The device of  claim 20 , wherein the operation parameter adjustment circuit comprises:
 at least one of an operation frequency control circuit for adjusting the operation frequency supplied to the integrated circuit body, a power supply voltage control circuit for adjusting the power supply voltage supplied to the integrated circuit body, and a substrate voltage control circuit for adjusting the substrate voltage supplied to the integrated circuit body; and   a command issuance circuit for controlling the operation frequency control circuit, the power supply voltage control circuit and the substrate voltage control circuit based on the measured parameter of the element to be measured for monitoring.   
   
   
       25 . The device of  claim 21 , wherein the operation parameter adjustment circuit comprises:
 at least one of an operation frequency control circuit for adjusting the operation frequency supplied to the integrated circuit body, a power supply voltage control circuit for adjusting the power supply voltage supplied to the integrated circuit body, and a substrate voltage control circuit for adjusting the substrate voltage supplied to the integrated circuit body; and   a command issuance circuit for controlling the operation frequency control circuit, the power supply voltage control circuit and the substrate voltage control circuit based on the measured parameter of the element to be measured for monitoring.   
   
   
       26 . The device of  claim 24 , wherein the command issuance circuit issues command signals in response to at least one of an instruction from an operating system, an instruction from application software, a signal inputted from outside, a signal from a memory and the processing load amount of the integrated circuit body, to control the operation frequency control circuit, the power supply voltage control circuit and the substrate voltage control circuit. 
   
   
       27 . The device of  claim 25 , wherein the command issuance circuit issues command signals in response to at least one of an instruction from an operating system, an instruction from application software, a signal inputted from outside, a signal from a memory and the processing load amount of the integrated circuit body, to control the operation frequency control circuit, the power supply voltage control circuit and the substrate voltage control circuit. 
   
   
       28 . The device of  claim 18 , wherein the monitor circuit includes a plurality of monitor circuits and the operation parameter adjustment circuit includes a plurality of operation parameter adjustment circuits, and
 the plurality of monitor circuits and the plurality of operation parameter adjustment circuits are placed on a same substrate.   
   
   
       29 . The device of  claim 19 , wherein the monitor circuit includes a plurality of monitor circuits and the operation parameter adjustment circuit includes a plurality of operation parameter adjustment circuits, and
 the plurality of monitor circuits and the plurality of operation parameter adjustment circuits are placed on a same substrate.   
   
   
       30 . The device of  claim 28 , wherein the integrated circuit body is composed of a plurality of circuit blocks,
 the plurality of monitor circuits and the plurality of operation parameter adjustment circuits are provided to correspond to the plurality of circuit blocks, and   at least one of the plurality of monitor circuits selects an element to be measured whose measured parameter value is in a rank different from that in the other monitor circuits as the element to be measured for monitoring.   
   
   
       31 . The device of  claim 29 , wherein the integrated circuit body is composed of a plurality of circuit blocks,
 the plurality of monitor circuits and the plurality of operation parameter adjustment circuits are provided to correspond to the plurality of circuit blocks, and   at least one of the plurality of monitor circuits selects an element to be measured whose measured parameter value is in a rank different from that in the other monitor circuits as the element to be measured for monitoring.   
   
   
       32 . The device of  claim 18 , wherein at least one of the monitor circuit and the operation parameter adjustment circuit is formed close to the integrated circuit body. 
   
   
       33 . The device of  claim 19 , wherein at least one of the monitor circuit and the operation parameter adjustment circuit is formed close to the integrated circuit body. 
   
   
       34 . The device of  claim 18 , further comprising a pad,
 wherein at least one of the monitor circuit and the operation parameter adjustment circuit is formed near the pad, or formed partly or entirely under the pad.   
   
   
       35 . The device of  claim 19 , further comprising a pad,
 wherein at least one of the monitor circuit and the operation parameter adjustment circuit is formed near the pad, or formed partly or entirely under the pad.   
   
   
       36 . The device of  claim 18 , wherein at least one of the monitor circuit and the operation parameter adjustment circuit is formed in the center of the substrate. 
   
   
       37 . The device of  claim 19 , wherein at least one of the monitor circuit and the operation parameter adjustment circuit is formed in the center of the substrate. 
   
   
       38 . The device of  claim 18 , further comprising a pad,
 wherein part or the entire of at least one of the plurality of elements to be measured for monitoring and part or the entire of the integrated circuit body are formed under the pad.   
   
   
       39 . The device of  claim 19 , further comprising a pad,
 wherein part or the entire of at least one of the plurality of elements to be measured for monitoring and part or the entire of the integrated circuit body are formed under the pad.

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