Chip-Stacked Package Structure

Abstract

A chip stacked package structure and applications are provided, wherein the chip stacked package structure comprises a substrate, a first chip, a patterned circuit layer and a second chip. The substrate has a first surface and an opposite second surface. The first chip with a first active area and an opposite first rear surface is electrically connected to first surface of substrate by a flip chip bonding process. The patterned circuit layer set on the dielectric layer is electrically connected to the substrate via a bonding wire. The second chip set on the patterned circuit layer has a second active area and a plurality of second pads formed on the second active area, wherein the second bonding pad is electrically connected to the patterned circuit layer.

1 . A chip-stacked package structure, comprising:
 a substrate with a first surface and a second surface opposite to the first surface, wherein the substrate has a through hole;   a first chip set on the first surface of the substrate, wherein the first chip comprises:
 a first active area and a first rear surface opposite to the first active area, and the first active area faces the substrate and the through hole of the substrate exposes a portion of the first active area; and 
 a plurality of first bonding pads set on the first active area and electrically connected to the substrate via a plurality of first bonding wires passing through the through hole; and 
   a second chip set on the first chip, wherein the second chip comprises:
 a second rear surface adhered to the first rear surface; 
 a second active area opposite to the second rear surface; 
 a plurality of second bonding pads set on the second active area; and 
 a patterned circuit layer set on the second active area and electrically connected to the substrate via a plurality of second bonding wires; 
 wherein the second bonding pads are electrically connected to the substrate via the patterned circuit layer and the second bonding wires. 
   
     
     
         2 . The chip-stacked package structure in accordance with  claim 1 , wherein the patterned circuit layer is a redistribution layer. 
     
     
         3 . The chip-stacked package structure in accordance with  claim 1 , wherein the patterned circuit layer has a plurality of fingers, each of the fingers has a first end electrically connected to a corresponding second bonding pad and a second end adjacent to one edge of the second chip and extended from the first end, and the second end is electrically connected with the second bonding wire. 
     
     
         4 . The chip-stacked package structure in accordance with  claim 1 , further comprising a plurality of external connecting bumps set on the second surface of the substrate. 
     
     
         5 . The chip-stacked package structure in accordance with  claim 4 , wherein the external connecting bumps are solder bumps. 
     
     
         6 . The chip-stacked package structure in accordance with  claim 1 , further comprising a molding compound covering the first chip, the first bonding wires, the second chip, the second bonding wires and the substrate.