Method of manufacturing a printed circuit board having embedded electronic components

Abstract

A method of manufacturing a printed circuit board having embedded electronic components. With the printed circuit board having embedded electronic components, including a core sheet, a first electronic component mounted on one side of the core sheet, a second electronic component mounted on the other side of the core sheet and overlapping the first electronic component, a first insulation layer stacked on one side of the core sheet and covering the first electronic component, a second insulation layer stacked on the other side of the core sheet and covering the second electronic component, and a circuit pattern formed on the surface of the first insulation layer or the second insulation layer, the density of the printed circuit board having embedded components is improved, as a plurality of electronic components are embedded simultaneously, and when a thin CCL substrate or a metal substrate is used as the core, a metal substrate in particular, the heat-releasing property and mechanical strength are improved, including increased bending strength in a thermal-stress environment, as electronic components are mounted on both sides of the core sheet.

1 . A method of manufacturing a printed circuit board having embedded electronic components, the method comprising:
 mounting a first electronic component on one side of a core sheet;   stacking a first insulation layer on one side of the core sheet such that the first insulation layer covers the first electronic component;   mounting a second electronic component on the other side of the core sheet such that the second electronic component overlaps the first electronic component;   stacking a second insulation layer on the other side of the core sheet such that the second insulation layer covers the second electronic component; and   forming a circuit pattern on a surface of the first insulation layer or the second insulation layer.   
     
     
         2 . A method of manufacturing a printed circuit board having embedded electronic components, the method comprising:
 mounting a first electronic component on one side of a core sheet and mounting a second electric component on the other side of the core sheet such that the second electronic component overlaps the first electronic component;   stacking a first insulation layer on one side of the core sheet such that the first insulation layer covers the first electronic component and stacking a second insulation layer on the other side of the core sheet such that the second insulation layer covers the second electronic component; and   forming a circuit pattern on a surface of the first insulation layer or the second insulation layer.   
     
     
         3 . The method of  claim 1 , further comprising flipping the core sheet so that the other side of the core sheet is turned to face one side of the core sheet, between said stacking the first insulation layer and said mounting the second electric component. 
     
     
         4 . The method according to  claim 1 , wherein the core sheet is a metal substrate. 
     
     
         5 . The method of  claim 4 , wherein the metal substrate includes aluminum (Al) or copper (Cu) or stainless steel (SS). 
     
     
         6 . The method according to  claim 1 , wherein the corer sheet is a copper clad laminate (CCL). 
     
     
         7 . The method according to  claim 1 , wherein the first electronic component and the second electronic component are identical in size and shape. 
     
     
         8 . The method according to  claim 1 , wherein the first electronic component and the second electronic component are mounted in symmetry with respect to the core sheet. 
     
     
         9 . The method according to  claim 1 , wherein the first electronic component or the second electronic component are mounted on the core sheet by way of chip adhesive applied in-between. 
     
     
         10 . The method according to  claim 1 , wherein the first insulation layer or the second insulation layer is prepreg (PPG) or Ajinomoto build-up film (ABF), and the circuit pattern is formed by stacking a copper foil layer on a surface of the first insulation layer or the second insulation layer. 
     
     
         11 . The method according to  claim 1 , wherein the first insulation layer and the second insulation layer are RCC. 
     
     
         12 . The method of  claim 1 , further comprising perforating at least one portion of the core sheet to form at least one core hole, before said stacking the second insulation layer, and further comprising forming at least one IVH penetrating the first insulation layer, the second insulation layer, and the core sheet, after said stacking the second insulation layer. 
     
     
         13 . The method of  claim 2 , further comprising perforating at least one portion of the core sheet to form at least one core hole, before said stacking the first insulation layer and stacking the second insulation layer, and further comprising forming at least one IVH penetrating the first insulation layer, the second insulation layer, and the core sheet, after said stacking the first insulation layer and stacking the second insulation layer. 
     
     
         14 . The method according to  claim 12 , wherein the core hole has a cross section greater than that of the IVH such as to allow the IVH to penetrate the core sheet. 
     
     
         15 . The method of  claim 14 , wherein a metal layer is formed on an inner perimeter of the IVH, and the metal layer is electrically connected with the circuit pattern. 
     
     
         16 . The method of  claim 1 , further comprising forming at least one first BVH (blind via hole) in the first insulation layer in correspondence with a position of at least one electrode of the first electronic component and forming at least one second BVH in the second insulation layer in correspondence with a position of at least one electrode of the second electronic component, after said stacking the second insulation layer. 
     
     
         17 . The method of  claim 2 , further comprising forming at least one first BVH (blind via hole) in the first insulation layer in correspondence with a position of at least one electrode of the first electronic component and forming at least one second BVH in the second insulation layer in correspondence with a position of at least one electrode of the second electronic component, after said stacking the first insulation layer and stacking the second insulation layer. 
     
     
         18 . The method according to  claim 16 , wherein a plating layer is formed on at least one surface of the at least one first BVH and the at least one second BVH. 
     
     
         19 . The method according to  claim 1 , further comprising stacking an insulation layer and a plating layer on the circuit pattern and forming an outer layer circuit on the plating layer. 
     
     
         20 . The method according to  claim 2 , wherein the core sheet is a metal substrate. 
     
     
         21 . The method according to  claim 2 , wherein the core sheet is a copper clad laminate (CCL). 
     
     
         22 . The method according to  claim 2 , wherein the first electronic component and the second electronic component are identical in size and shape. 
     
     
         23 . The method according to  claim 2 , wherein the first electronic component and the second electronic component are mounted in symmetry with respect to the core sheet. 
     
     
         24 . The method according to  claim 2 , wherein the first electronic component or the second electronic component are mounted on the core sheet by way of chip adhesive applied in-between. 
     
     
         25 . The method according to  claim 2 , wherein the first insulation layer or the second insulation layer is prepreg (PPG) or Ajinomoto build-up film (ABF), and the circuit pattern is formed by stacking a copper foil layer on a surface of the first insulation layer or the second insulation layer. 
     
     
         26 . The method according to  claim 2 , wherein the first insulation layer and the second insulation layer are RCC. 
     
     
         27 . The method according to  claim 13 , wherein the core hole has a cross section greater than that of the IVH such as to allow the IVH to penetrate the core sheet. 
     
     
         28 . The method according to  claim 17 , wherein a plating layer is formed on at least one surface of the at least one first BVH and the at least one second BVH. 
     
     
         29 . The method according to  claim 2 , further comprising stacking an insulation layer and a plating layer on the circuit pattern and forming an outer layer circuit on the plating layer. 
     
     
         30 . The method according to  claim 2 , wherein the core sheet is a metal substrate. 
     
     
         31 . The method according to  claim 2 , wherein the core sheet is a copper clad laminate (CCL). 
     
     
         32 . The method according to  claim 2 , wherein the first electronic component and the second electronic component are identical in size and shape. 
     
     
         33 . The method according to  claim 2 , wherein the first electronic component and the second electronic component are mounted in symmetry with respect to the core sheet. 
     
     
         34 . The method according to  claim 13 , wherein the core hole has a cross section greater than that of the IVH such as to allow the IVH to penetrate the core sheet. 
     
     
         35 . The method according to  claim 17 , wherein a plating layer is formed on at least one surface of the at least one first BVH and the at least one second BVH. 
     
     
         36 . The method according to  claim 2 , further comprising stacking an insulation layer and a plating layer on the circuit pattern and forming an outer layer circuit on the plating layer.