Semiconductor memory device having selective activation circuit for selectively activating circuit areas

Abstract

A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.

1 . A semiconductor memory device comprising:
 a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of the memory banks being selected by a corresponding bank selective signal; and   a selective activation circuit that activates any one of the circuit areas and deactivates at least one of remaining circuit areas based on the address signal included in a memory bank that is selected based on the bank selective signal.   
     
     
         2 . The semiconductor memory device as claimed in  claim 1 , wherein
 each of the circuit areas includes a main power source line, a sub power source line, a switch circuit connected between the main power source line and the sub power source line, and a logic circuit connected to the main power source line and the sub power source line, and   the selective activation circuit turns on the switch circuit that is included in a circuit area to be activated, and turns off the switch circuit included in a circuit area to be deactivated based on the address signal and the bank selective signal.   
     
     
         3 . The semiconductor memory device as claimed in  claim 2 , wherein the main power source lines provided in the circuit areas are commonly connected to each other and the sub power source lines provided in the circuit areas are provided separately from one another. 
     
     
         4 . The semiconductor memory device as claimed in  claim 1 , wherein
 each of the circuit areas includes a word driver, and   the selective activation circuit activates a selected word driver and deactivates remaining word drivers based on a row address signal included in the address signal and the bank selective signal.   
     
     
         5 . The semiconductor memory device as claimed in  claim 4 , further comprising a row pre-decoder that generates a pre-decode signal by decoding a part of the row address signal, wherein
 each bit of the pre-decode signal is associated one of the word drivers included in each of the circuit areas, and   the selective activation circuit controls activation and deactivation of the word driver based on the pre-decode signal and the bank selective signal.   
     
     
         6 . The semiconductor memory device as claimed in  claim 5 , wherein
 each of the circuit areas further includes a sense amplifier controller that is selected even when any one of associated two or more pre-decode signals is in an active state, and   the selective activation circuit activates a selected sense amplifier controller and deactivates remaining amplifier controllers based on the pre-decode signal and the bank selective signal.   
     
     
         7 . The semiconductor memory device as claimed in  claim 5 , wherein
 the bank selective signal is activated in response to an input of the row address signal and deactivated in response to completion of a sense operation of the memory bank, and   the selective activation circuit activates a word driver with at least one of the bank selective signal and the corresponding pre-decode signal in an activation state.   
     
     
         8 . The semiconductor memory device as claimed in  claim 1 , wherein
 each of the circuit areas includes a column select circuit, and   the selective activation circuit controls activation and deactivation of the column select circuit based on a column address signal included in the address signal and the bank selective signal.   
     
     
         9 . The semiconductor memory device as claimed in  claim 1 , wherein
 the circuit area activated by the selective activation circuit generates an output signal in an active state when the address signal indicating a predetermined value and generates the output signal in an inactive state when the address signal indicating a different value from the predetermined value, and   the circuit area deactivated by the selective activation circuit generates the output signal in the inactive state regardless of the address signal.   
     
     
         10 . A semiconductor memory device comprising:
 a memory bank that includes a plurality of memory cells each connected to an associated one of word lines and an associated one of bit lines;   a row decoder that includes a plurality of word drivers and performs selection of the word lines based on a row address;   a column decoder that performs selection of the bit lines based on a column address; and   a selective activation circuit that activates any one of the word drivers and deactivates remaining word drivers based on the row address, wherein   each of the word drivers includes a main power source line, a sub power source line, a switch circuit connected between the main power source line and the sub power source line, and a logic circuit that is connected to the main power source line and the sub power source line, and   the selective activation circuit turns on the switch circuit that is included in one of the word drivers to be activated, and turns off the switch circuit included in the remaining word drivers to be deactivated.   
     
     
         11 . The semiconductor memory device as claimed in  claim 10 , wherein the selective activation circuit once activates all of the word drivers regardless of which one of the word drivers is to be activated, and then deactivates the remaining word drivers. 
     
     
         12 . The semiconductor memory device as claimed in  claim 11 , wherein the selective activation circuit deactivates the rest of the word drivers in response to completion of a sense operation of the memory bank. 
     
     
         13 . A semiconductor memory device comprising:
 a plurality of memory banks each including a plurality of memory cell arrays, a plurality of control circuits provided correspondingly to the memory cell arrays, and a power source line supplied with a power voltage;   a plurality of address terminals receiving address signals respectively, the address signals including one or more bank address signals and a plurality of cell address signals; and   a bank control circuit decoding the bank address signals and outputting decoded bank address signals to select at least one of the memory banks, wherein   each of the memory banks further includes a decoding circuit decoding the cell address signals and outputting decoded cell address signals to select one of the control circuits,   each of the control circuits includes an internal source line and a switch, and   the switch of one of the control circuits, which is selected by the decoded cell address signals and contained in one of the memory banks selected by the decoded bank address signals, is turned ON to electrically connect the power source line and the internal source line.   
     
     
         14 . A semiconductor memory device comprising:
 a plurality of memory banks each including a plurality of memory cell arrays, a plurality of control circuits provided correspondingly to the memory cell arrays, and a power source line supplied with a power voltage;   a plurality of address terminals receiving address signals respectively, the address signals including one or more bank address signals and a plurality of cell address signals;   a bank control circuit decoding the bank address signals and outputting decoded bank address signals to select at least one of the memory banks; and   a decoding circuit decoding the cell address signals and outputting decoded cell address signals to at least one of the memory banks to select one of the control circuits in associated one or ones of the memory banks, wherein   each of the control circuits includes an internal source line and a switch, and   the switch of one of the control circuits, which is selected by the decoded cell address signals and contained in one of the memory banks selected by the decoded bank address signals, being turned ON to electrically connect the power source line and the internal source line.