Semiconductor device storage cell structure, method of operation, and method of manufacture

Abstract

A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and forming a control gate terminal from at least a portion of a semiconductor layer deposited on a substrate surface in contact with the channel region, the portion of the semiconductor layer being doped to the second conductivity type.

1 . A semiconductor device, comprising:
 at least one storage cell, comprising   a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type;   at least a first source/drain region and a second source/drain region separated from one another by the channel region; and   a control gate structure, comprising a semiconductor layer doped to the first conductivity type and formed over a substrate surface, the control gate structure being in contact with the channel region; wherein   the store gate is formed on the substrate surface.   
   
   
       2 . A semiconductor device, comprising:
 at least one storage cell, comprising   a store gate structure formed from a semiconductor material doped to a first conductivity type and in contact with a channel region comprising a semiconductor material doped to a second conductivity type;   at least a first source/drain region and a second source/drain region separated from one another by the channel region; and   a control gate structure, comprising a semiconductor layer doped to the first conductivity type and formed over a substrate surface, the control gate structure being in contact with the channel region; wherein   the control gate structure is formed adjacent to the store gate structure in a direction parallel to the substrate surface.   
   
   
       3 . An integrated circuit operating method, comprising the steps of:
 storing a first predetermined value in at least a first storage cell by applying a first gate voltage to a gate terminal of the first storage cell and a first source voltage to a source of the storage cell, the gate terminal comprising a semiconductor material doped to a first conductivity type and formed on a substrate surface, the first gate and source voltages creating a punchthrough voltage through a semiconductor region of a second conductivity type that charges a store gate comprising a semiconductor material doped to the first conductivity type; and   determining the data value stored in the storage cell according to the magnitude of a current flowing through a channel region of the first storage cell, the channel region comprising a semiconductor material doped to the second conductivity type that is adjacent to the store gate.   
   
   
       4 . The integrated circuit operating method of  claim 3 , wherein:
 storing the first predetermined value in the first storage cell further includes applying a reference voltage to at least a first source/drain structure of the first storage cell, the first source/drain structure comprising a semiconductor material doped to the second conductivity type and in contact with the channel region of the first storage cell.   
   
   
       5 . The integrated circuit operating method of  claim 3 , further including:
 preventing the predetermined value from being stored in a second storage cell, having the first write voltage applied to its gate terminal, by applying a write inhibit voltage to at least a first source/drain region of the second storage cell, the first source/drain structure comprising a semiconductor material doped to the second conductivity type and in contact with the channel region of the second storage cell, the write inhibit voltage preventing punchthrough from occurring between the gate terminal and a store gate of the second storage cell.   
   
   
       6 . The integrated circuit operating method of  claim 3 , wherein:
 determining the data value stored in the first storage cell includes applying a bias voltage to a first source/drain structure of the first storage cell, the first source/drain structure comprising a semiconductor material doped to the second conductivity type and in contact with the channel region of the first storage cell.   
   
   
       7 . The integrated circuit operating method of  claim 6 , further including:
 preventing a second storage cell, having a first source/drain structure commonly connected to the first source/drain structure of the first storage cell, from adversely affecting the determination of the data value stored in the first storage cell by placing a second source/drain structure of the second storage cell into a high impedance state.   
   
   
       8 . The integrated circuit operating method of  claim 6 , further including:
 preventing a second storage cell, having a first source/drain structure commonly connected to the first source/drain structure of the first storage cell, from adversely affecting the determination of the data value stored in the first storage cell by applying a read inhibit voltage to a gate terminal of the second storage cell that increases an impedance in a channel region of the second storage cell without punching through to a store gate of the second storage cell.   
   
   
       9 . The integrated circuit operating method of  claim 3 , further including:
 storing a second predetermined value in the first storage cell by applying a second write voltage to at least a first source/drain structure of the first storage cell, the first source/drain structure comprising a semiconductor material doped to the second conductivity type and in contact with the channel region of the first storage cell, the second write voltage forward biasing a pn junction created by the store gate, the channel region and the first source/drain structure.   
   
   
       10 . The integrated circuit operating method of  claim 3 , further including:
 storing a second predetermined value in the first storage cell by applying a third write voltage to at least a first source/drain structure of the first storage cell, the first source/drain structure comprising a semiconductor material doped to the second conductivity type and in contact with the channel region of the first storage cell, the third write voltage changing a charge path, comprising a semiconductor material doped to the first conductivity type, from a pinch-off state to a conducting state.   
   
   
       11 . A method of fabricating an integrated circuit device storage cell, comprising:
 forming a channel region comprising a semiconductor material doped to a first conductivity type;   forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and   forming a control gate terminal from at least a portion of a semiconductor layer deposited on a substrate surface in contact with the channel region, the portion of the semiconductor layer being doped to the second conductivity type.   
   
   
       12 . The method of  claim 11 , wherein:
 the substrate comprises a semiconductor material;   forming the channel region includes doping a portion of the substrate to a predetermined depth with impurities of the first conductivity type; and   forming the store gate includes doping a region within the channel region with impurities of the second conductivity type.   
   
   
       13 . The method of  claim 12 , further including:
 forming an isolation structure;   forming the channel region includes forming the channel region within an area defined by the isolation structure; and   forming the store gate includes doping a region within the channel region that extends from one side of the isolation structure to an opposing side of the isolation structure.   
   
   
       14 . The method of  claim 11 , wherein:
 forming the store gate includes doping a region within the channel region with impurities of the second conductivity type, where the region is surrounded by portions of the channel region doped to the first conductivity type.   
   
   
       15 . The method of  claim 11 , further including:
 depositing the semiconductor layer on the substrate surface;   doping at least one portion of the semiconductor layer to the first conductivity type;   doping at least another portion of the semiconductor layer to the second conductivity type; and   patterning the semiconductor layer to form the control gate terminal and at least a first source/drain terminal, the first source/drain terminal being doped to the first conductivity type.   
   
   
       16 . The method of  claim 11 , further including:
 forming the channel region includes doping a bulk portion of a semiconductor substrate doped to the second conductivity type with impurities of the first conductivity type;   forming a discharge path within the channel region and in contact with the bulk portion by doping a portion of the channel region with impurities of the second conductivity type; and   forming the store gate structure to be contact with the discharge path, but not in contact with the bulk portion.   
   
   
       17 . The method of  claim 11 , wherein:
 the semiconductor layer comprises silicon.