Ethernet system

Abstract

Four (4) unshielded twisted pairs of wires connect a hub and a computer in an Ethernet system: one (1) pair for transmission only, another for reception only and the other two (2) for transmission and reception. The signals in the wires are in packets each having timing signals defining a preamble and thereafter having digital signals representing information as by individual ones of three (3) amplitude levels. The signals received at the computer are provided with an automatic gain control (AGC) and then with digital conversions at a particular rate. A control loop operative upon the digital conversions regulates the AGC gain at a particular value. An equalizer operative only during the occurrence of the digital signals in each packet selects an individual one of the three (3) amplitude levels closest to the amplitude of each digital conversion at the time assumed to constitute the conversion peak. The amplitudes of the timing signals in each preamble at the times assumed to constitute the peaks and zero crossings of such signals are multiplied. The rate of such digital conversions is adjusted in accordance with the polarity and magnitude of the multiplication product. The relative amplitudes of the successive equalizer values following each preamble are evaluated at the times assumed to be the peaks of the digital conversions. The rate of the digital conversions is adjusted in accordance with such evaluations, thereby further regulating the digital conversions at the particular rate. The equalizer thus operates on the information signals in each packet at the signal peaks.

1 - 103 . (canceled) 
   
   
       104 . Apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, the apparatus comprising:
 an analog to digital converter arranged to convert the first discrete analog signal level to a corresponding digital first information signal, to convert the second discrete analog signal level to a corresponding digital second information signal, to convert the third discrete analog signal level to a corresponding digital third information signal, to convert the fourth analog signal level to a corresponding digital fourth information signal, to convert the fifth discrete analog signal level to a corresponding digital fifth information signal, to convert the sixth discrete analog signal level to a corresponding digital sixth information signal, to convert the seventh discrete analog signal level to a corresponding digital seventh information signal, to convert the eighth discrete analog signal level to a corresponding digital eighth information signal and to convert the ninth discrete analog signal level to a corresponding digital ninth information signal; and   circuitry arranged to individually identify each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels, to shift in time the first information signal relative to the first discrete analog signal level, to shift in time the second information signal relative to the second discrete analog signal level, to shift in time the third information signal relative to the third discrete analog signal level, to shift in time the fourth information signal relative to the fourth discrete analog signal level, to shift in time the fifth information signal relative to the fifth discrete analog signal level, to shift in time the sixth information signal relative to the sixth discrete analog signal level, to shift in time the seventh information signal relative to the seventh discrete analog signal level, to shift in time the eighth information signal relative to the eighth discrete analog signal level and to shift in time the ninth information signal relative to the ninth discrete analog signal level.   
   
   
       105 . The apparatus of  claim 104 , wherein the analog to digital converter is arranged to convert the discrete analog signals levels to corresponding digital information signals at a particular rate and wherein the circuitry comprises a timing recovery circuit arranged to regulate the particular rate at which said analog to digital converter converts the discrete analog signal levels. 
   
   
       106 . The apparatus of  claim 105 , wherein the circuitry comprises a digital adaptive equalizer arranged to identify the discrete analog signal level being received on each of the wire pairs. 
   
   
       107 . The apparatus of  claim 106 , further comprising an automatic gain control circuit coupled to the analog to digital converter. 
   
   
       108 . The apparatus of  claim 106 , further comprising a decoder circuit coupled to the digital adaptive equalizer. 
   
   
       109 . The apparatus of  claim 108 , further comprising a media access controller coupled to said decoder circuit. 
   
   
       110 . The apparatus of  claim 106 , wherein the digital adaptive equalizer includes a feedforward equalizer, a data slicer and a decision feedback equalizer. 
   
   
       111 . The apparatus of  claim 106 , wherein said timing recovery circuit regulates the particular rate in accordance with a product of a plurality of signal samples. 
   
   
       112 . The apparatus of  claim 104 , further comprising a clock arranged to generate clock signals having a phase and wherein the analog to digital converter is arranged to convert the discrete analog signal levels to the corresponding digital information digital signals in response to the clock signals and wherein the circuitry is arranged to shift the phase of the clock signals so that the time at which the analog to digital converter samples the discrete analog signal levels is adjusted. 
   
   
       113 . The apparatus of  claim 112 , wherein the circuitry shifts the phase of the clock signals in accordance with a product of a plurality of signal samples. 
   
   
       114 . The apparatus of  claim 112 , wherein each of the wire pairs enables receipt of timing discrete analog signal levels, wherein the analog to digital converter is arranged to convert the timing discrete analog signal levels to corresponding timing digital signals in response to the clock signals, and wherein the circuitry is arranged to shift the phase of the clock signals in response to the timing digital signals. 
   
   
       115 . The apparatus of  claim 114 , wherein the circuitry is arranged to shift the phase of the clock signals in response to both the timing digital signals and the information digital signals. 
   
   
       116 . In apparatus adapted to be coupled to at least a twisted first wire pair enabling receipt of at least first, second and third discrete analog signal levels with different amplitudes representing information, a twisted second wire pair enabling receipt of at least fourth, fifth and sixth discrete analog signal levels with different amplitudes representing information and a twisted third wire pair enabling receipt of at least seventh, eighth and ninth discrete analog signal levels with different amplitudes representing information, the analog signal levels being received one discrete signal level at a time, a method of processing the received discrete analog signal levels comprising:
 converting the first discrete analog signal level to a corresponding digital first information signal;   converting the second discrete analog signal level to a corresponding digital second information signal;   converting the third discrete analog signal level to a corresponding digital third information signal;   converting the fourth discrete analog signal level to a corresponding digital fourth information signal;   converting the fifth discrete analog signal level to a corresponding digital fifth information signal;   converting the sixth discrete analog signal level to a corresponding digital sixth information signal;   converting the seventh discrete analog signal level to a corresponding digital seventh information signal;   converting the eighth discrete analog signal level to a corresponding digital eighth information signal;   converting the ninth discrete analog signal level to a corresponding digital ninth information signal;   individually identifying each of the first, second, third, fourth, fifth, sixth, seventh, eighth and ninth discrete analog signal levels;   shifting in time the first information signal relative to the first discrete analog signal level;   shifting in time the second information signal relative to the second discrete analog signal level;   shifting in time the third information signal relative to the third discrete analog signal level;   shifting in time the fourth information signal relative to the fourth discrete analog signal level;   shifting in time the fifth information signal relative to the fifth discrete analog signal level;   shifting in time the sixth information signal relative to the sixth discrete analog signal level;   shifting in time the seventh information signal relative to the seventh discrete analog signal level;   shifting in time the eighth information signal relative to the eighth discrete analog signal level; and   shifting in time the ninth information signal relative to the ninth discrete analog signal level.   
   
   
       117 . The method of  claim 116 , wherein each of the converting steps comprises converting one of the discrete analog signals levels to a corresponding one of the information signals at a particular rate and further comprising regulating the particular rate. 
   
   
       118 . The method of  claim 117 , wherein said regulating comprises regulating the particular rate in accordance with a product of a plurality of signal samples. 
   
   
       119 . The method of  claim 116 , further comprising controlling the gain of the each of the received discrete analog signal levels. 
   
   
       120 . The method of  claim 116 , further comprising decoding each of the digital information signals. 
   
   
       121 . The method of  claim 116 , further comprising controlling media access. 
   
   
       122 . The method of  claim 116 , further comprising generating clock signals having a phase and wherein each of the converting steps comprises converting one of the discrete analog signal levels to one of the corresponding digital information signals in response to the clock signals and wherein each of the shifting steps comprises shifting the phase of the clock signals so that the time at which the converting occurs is adjusted. 
   
   
       123 . The method of  claim 122 , wherein the shifting comprises shifting the phase of the clock signals in accordance with a product of a plurality of signal samples. 
   
   
       124 . The method of  claim 122 , wherein each of the wire pairs enables receipt of timing discrete analog signal levels, wherein the converting comprises converting the timing discrete analog signal levels to corresponding timing digital signals in response to the clock signals, and wherein the shifting comprises shifting the phase of the clock signals in response to the timing digital signals. 
   
   
       125 . The method of  claim 124 , wherein the shifting comprises shifting the phase of the clock signals in response to both the timing digital signals and the digital information signals. 
   
   
       126 . A communication system for decoding signals having three or more analog signal levels to represent information transmitted by a first computer over a plurality of pairs of twisted wires to a second computer, said communication system including a transceiver comprising:
 a plurality of receivers and transmitters operatively coupled to respective ones of said plurality of said pairs of twisted wires, wherein each of said plurality of receivers comprises:   an analog to digital converter;   an automatic gain control circuit; and   a digital adaptive equalizer that includes a feed forward equalizer, a decision feedback equalizer and a data slicer,   wherein each of said analog to digital converters sampling said analog signal at a sampling rate, each of said automatic gain control circuits receiving said analog signal from one of said pairs of twisted wires and providing gain control at the input to a respective one of said analog to digital converters, and each of said equalizers producing recovered digital data from said sampled analog signal provided at the input of said equalizer, and   wherein said transceiver includes a plurality of transmitters that simultaneously transmit three or more analog signal levels to said first computer over said plurality of pairs of twisted wires.   
   
   
       127 . The system of  claim 126 , wherein said transceiver combines said recovered data from each of said digital adaptive equalizers into a single recovered digital data stream. 
   
   
       128 . The system of  claim 127 , wherein said single recovered data stream is Ethernet data. 
   
   
       129 . The system of  claim 126 , wherein said communication system is an Ethernet system. 
   
   
       130 . The system of  claim 126 , wherein the digital data is Ethernet data with a data rate of at least 100 Mbps. 
   
   
       131 . The system of  claim 126 , wherein each of said equalizer includes an adder that sums the output of respective ones of said decision feedback equalizers and said feed forward equalizers. 
   
   
       132 . The system of  claim 131 , wherein the digital data is Ethernet data. 
   
   
       133 . A computer network device, comprising:
 transmitting circuitry including an encoder and data splitter circuitry, a first transmitter, a second transmitter and a third transmitter, wherein the first transmitter, the second transmitter and the third transmitter are coupled to a network via a respective pair of twisted wires;   receiving circuitry including clock recover circuitry, data combiner and decoder circuitry, a first receiver and equalizer, a second receiver and equalizer and a third receiver and equalizer, wherein the clock recover circuitry is disposed along a data path between the receivers and equalizers and the data combiner and decoder circuitry, wherein the first receiver and equalizer, the second receiver and equalizer and the third receiver and equalizer is coupled to the network via a respective pair of twisted wires;   a media access control coupled to a system bus, the encoder and data splitter circuitry of the transmitting circuitry and the data combiner and decoder circuitry of the receiver circuitry; and   collision detect and link control circuitry coupled to the media access control, the transmitters and the receivers and equalizers,   wherein the first receiver and equalizer comprises an automatic gain control stage, an analog-to-digital converter and a digital adaptive equalizer, wherein the automatic gain control state is coupled to the analog-to-digital converter, and wherein the analog-to-digital converter is coupled to the digital adaptive equalizer.   
   
   
       134 . The computer network device according to  claim 133 , wherein the digital adaptive equalizer comprises a feed forward equalizer, a three-level data slicer and a decision feedback equalizer. 
   
   
       135 . The computer network device according to  claim 134 , wherein the digital adaptive equalizer comprises an adder that has a first input, a second input and an output, wherein the first input is coupled to the feed forward equalizer, wherein the second input is coupled to the decision feedback equalizer and wherein the output is coupled to the three-level data slicer. 
   
   
       136 . The computer network device according to  claim 134 , wherein first receiver and equalizer comprises timing recovery circuitry, wherein timing recover circuitry comprises a low gain error generator, a high gain error generator, a loop filter, a phase inverter and a controller.