US2010148848A1PendingUtilityA1

High speed four-to-one multiplexer

43
Assignee: BROADCOM CORPPriority: May 30, 2007Filed: Feb 8, 2010Published: Jun 17, 2010
Est. expiryMay 30, 2027(~0.8 yrs left)· nominal 20-yr term from priority
Inventors:Paul Penzes
H03K 17/005
43
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Claims

Abstract

According to one embodiment, a high speed multiplexer includes a number of data inputs, a number of hot code select inputs, and a final data output. In one embodiment, the high speed multiplexer utilizes a number of intermediate multiplexers, each receiving respective hot code select inputs and providing an intermediate data output. In one embodiment, each intermediate multiplexer has a critical delay path comprising a first NAND gate and a second NAND gate. In one implementation a four-to-one intermediate multiplexer comprises a first two-input NAND gate and a second four-input NAND gate. In one embodiment, a 32-to-1 high speed multiplexer comprises four four-to-one intermediate multiplexers. According to one implementation of this embodiment, the 32-to-1 multiplexer has a critical delay path from any of the data inputs to the final data output comprising a first NAND gate, a second NAND gate, a NOR gate, and a third NAND gate.

Claims

exact text as granted — not AI-modified
1 - 15 . (canceled) 
   
   
       16 . A high speed four-to-one multiplexer comprising:
 four data inputs;   four hot code select inputs, wherein only one of said four hot code select inputs is valid;   a data output;   a critical delay path from any of said four data inputs to said data output, said critical delay path including a first NAND gate and a second NAND to reduce a data propagation delay in said high speed four-to-one multiplexer.   
   
   
       17 . The high speed multiplexer of  claim 16  wherein said first NAND gate is a two-input NAND gate, and said second NAND gate is a four-input NAND gate. 
   
   
       18 . The high speed multiplexer of  claim 16  wherein said multiplexer is utilized in a 32-to-1 multiplexer. 
   
   
       19 . The high speed multiplexer of  claim 16  wherein said multiplexer is utilized in a 24-to-1 multiplexer. 
   
   
       20 . The high speed multiplexer of  claim 16  wherein said multiplexer is utilized in a Scoreboard unit of a CPU. 
   
   
       21 . A high speed four-to-one multiplexer comprising:
 four data inputs;   a plurality of hot code select inputs;   at least one data output;   a critical delay path from any of said four data inputs to said data output, said critical delay path including at least two NAND gates to reduce a data propagation delay in said high speed four-to-one multiplexer.   
   
   
       22 . The high speed multiplexer of  claim 21  wherein said at least two NAND gates comprise at least one two-input NAND gate. 
   
   
       23 . The high speed multiplexer of  claim 21  wherein said at least two NAND gates comprise at least one four-input NAND gate. 
   
   
       24 . The high speed multiplexer of  claim 21  wherein said multiplexer is utilized in a 32-to-1 multiplexer. 
   
   
       25 . The high speed multiplexer of  claim 21  wherein said multiplexer is utilized in a 24-to-1 multiplexer. 
   
   
       26 . The high speed multiplexer of  claim 21  wherein said multiplexer is utilized in a Scoreboard unit of a CPU. 
   
   
       27 . A high speed four-to-one multiplexer comprising:
 four data inputs;   four hot code select inputs, wherein only one of said four hot code select inputs is valid;   a data output;   a critical delay path from any of said four data inputs to said data output, said critical delay path including at least two NAND gates and at least one NOR gate to reduce a data propagation delay in said high speed multiplexer.   
   
   
       28 . The high speed multiplexer of  claim 27  wherein said at least two NAND gates comprise at least one two-input NAND gate. 
   
   
       29 . The high speed multiplexer of  claim 27  wherein said at least two NAND gates comprise at least one four-input NAND gate. 
   
   
       30 . The high speed multiplexer of  claim 27  wherein said NOR gate is a is a two-input NOR gate. 
   
   
       31 . The high speed multiplexer of  claim 27  wherein said multiplexer is utilized in a 32-to-1 multiplexer. 
   
   
       32 . The high speed multiplexer of  claim 27  wherein said multiplexer is utilized in a 24-to-1 multiplexer. 
   
   
       33 . The high speed multiplexer of  claim 27  wherein said multiplexer is utilized in a Scoreboard unit of a CPU.

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