Semiconductor integrated circuit device and method for designing the same

Abstract

The layout of an LSI is previously designed so that cells below pads which will be affected by stress are arranged so that the occurrence of a malfunction of the LSI which will be caused by the influence of stress is reduced or prevented. In addition to or instead of the cell arrangement, the arrangement of pads, bumps or the like may be adjusted.

1 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip;   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads;   a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur; and   a second type cell formed in the semiconductor chip and configured to cause the semiconductor chip to perform erroneous operation if variations in timing occur,   
     wherein
 the density of the first type cells is higher than the density of the second type cells in an internal region of the semiconductor chip located below each of the plurality of pads. 
 
   
   
       2 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first type cell is provided in the internal regions while the second type cell is not provided in the internal regions.   
   
   
       3 . The semiconductor integrated circuit device of  claim 1 , wherein
 the second type cell is provided in the semiconductor chip excluding the internal regions.   
   
   
       4 . A method for designing a semiconductor integrated circuit device, 
     wherein
 the semiconductor integrated circuit device is of  claim 1 , and 
 the method comprises the step of:
 arranging the first type cell, with priority, in the internal regions using layout data after pad arrangement. 
 
 
   
   
       5 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 1 , and   the method comprises the step of:
 arranging the second type cell using layout data before pad arrangement, and thereafter, arranging the plurality of pads in accordance with a constraint which prohibits overlapping with the second type cell. 
   
   
   
       6 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip;   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads; and   a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur,   
     wherein
 the density of the first type cells is higher than or equal to a predetermined value in an internal region of the semiconductor chip located below one of the plurality of pads that is electrically connected to one of the plurality of input/output cells. 
 
   
   
       7 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 6 , and   the method comprises the step of:
 when at least two pads are electrically connected to the same input/output cell in layout data after pad arrangement, calculating the degree of overlapping between each of the at least two pads and the first type cell, and removing one having a relatively low degree of overlapping of the at least two pads. 
   
   
   
       8 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip;   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads; and   a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur,   
     wherein
 at least two of the plurality of pads are electrically connected to the same input/output cell, and 
 a bump is selectively provided on one of the at least two pads that has a relatively high density of the first type cells provided in an internal region of the semiconductor chip located therebelow. 
 
   
   
       9 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 8 , and   the method comprises the step of:
 when at least two pads are electrically connected to the same input/output cell in layout data after pad arrangement, calculating the degree of overlapping between each of the at least two pads and the first type cell, and removing a bump from one having a relatively low degree of overlapping of the at least two pads. 
   
   
   
       10 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip;   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads; and   a first type cell formed in the semiconductor chip and configured not to cause the semiconductor chip to perform erroneous operation even if variations in timing occur,   
     wherein
 at least two of the plurality of pads are electrically connected to the same input/output cell, and 
 on one of the at least two pads that has a relatively low density of the first type cells provided in an internal region of the semiconductor chip located therebelow, a bump having a smaller diameter than those of bumps on the other pads is formed. 
 
   
   
       11 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 10 , and   the method comprises the step of:
 when at least two pads are electrically connected to the same input/output cell in layout data after pad arrangement, calculating the degree of overlapping between each of the at least two pads and the first type cell, and causing a diameter of a bump on one having a relatively low degree of overlapping of the at least two pads to be smaller than those of bumps on the other pads. 
   
   
   
       12 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first type cell is at least one of an ESD protective cell, an area ratio adjustment cell, a power supply capacitance cell, an input tie-fixed cell, and a level shifter.   
   
   
       13 . The semiconductor integrated circuit device of  claim 12 , wherein
 the input tie-fixed cell is a tie cell or a bonus cell.   
   
   
       14 . The semiconductor integrated circuit device of  claim 1 , wherein
 the second type cell is at least one of a standard cell, an analog cell, a processor core, and a memory core.   
   
   
       15 . The semiconductor integrated circuit device of  claim 1 , wherein
 the surface of the semiconductor chip is covered with a passivation layer having an opening portion on each of the plurality of pads,   a metal plating layer is formed on each of the plurality of pads so that the opening portion is filled with the metal plating layer, and   a bump is formed on the metal plating layer.   
   
   
       16 . The semiconductor integrated circuit device of  claim 15 , wherein
 a range within which the internal region is set is the same as a range within which each of the plurality of pads is formed.   
   
   
       17 . The semiconductor integrated circuit device of  claim 15 , wherein
 a range within which the internal region is set is the same as a range within the opening portion is formed.   
   
   
       18 . The semiconductor integrated circuit device of  claim 15 , wherein
 a range within which the internal region is set is the same as a range within a bonding portion between the metal plating layer and the bump is formed.   
   
   
       19 . The semiconductor integrated circuit device of  claim 15 , wherein
 a range within which the internal region is set is the same as a range within the bump is formed.   
   
   
       20 . The semiconductor integrated circuit device of  claim 15 , wherein
 a range within which the internal region is set is the same as a range within the metal plating layer is formed.   
   
   
       21 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip; and   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,   
     wherein
 all of the plurality of pads are electrically connected to the wire. 
 
   
   
       22 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 21 , and   the method comprises the step of:
 removing a pad which is not electrically connected to the wire, using layout data after pad arrangement. 
   
   
   
       23 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip; and   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,   
     wherein
 a bump is selectively provided on one of the plurality of pads that is electrically connected to the wire. 
 
   
   
       24 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 23 , and   the method comprises the step of:
 removing a bump from a pad which is not electrically connected to the wire, using layout data after pad arrangement. 
   
   
   
       25 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip; and   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,   
     wherein
 on one of the plurality of pads that is not electrically connected to the wire, a bump having a smaller diameter than those of bumps on the other pads is formed. 
 
   
   
       26 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 25 , and   the method comprises the step of:
 causing a diameter of a bump on one of the plurality of pads that is not electrically connected to the wire to be smaller than those of bumps on the other pads, using layout data after pad arrangement. 
   
   
   
       27 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip; and   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,   
     wherein
 of the plurality of input/output cells, the plurality of pads and the wire, an input/output cell, a pad and a wire which are provided in one hierarchical block are arranged so that the one hierarchical block can be operated singly. 
 
   
   
       28 . A method for designing a semiconductor integrated circuit device, wherein
 the semiconductor integrated circuit device is of  claim 27 , and   the method comprises the step of:
 arranging an input/output cell, a pad and a wire in one hierarchical block so that the one hierarchical block can be operated singly, using layout data after pad arrangement. 
   
   
   
       29 . A semiconductor integrated circuit device comprising:
 a semiconductor chip including a plurality of input/output cells;   a plurality of pads formed on a surface of the semiconductor chip; and   a wire formed on the surface of the semiconductor chip and configured to electrically connect at least one of the plurality of input/output cells and at least one of the plurality of pads,   
     wherein
 the surface of the semiconductor chip is covered with a passivation layer having an opening portion on each of the plurality of pads, and 
 the opening portion is in the shape of a polygon having four or more corners or a circle.