Microprocessors with improved power efficiency

Abstract

A microprocessor is arranged to process instructions at least some of which contain at least one immediate value which forms an operand of the function, wherein said immediate value is represented in a format which achieves a greater power efficiency than two's complement when said instructions are processed.

1 . A microprocessor arranged to process instructions at least some of which contain at least one immediate value which forms an operand of the function, said immediate value being represented in a format which achieves a greater power efficiency than two's complement when said instructions are processed;
 wherein said format is a variant sign magnitude format in which:   (a) non-negative values (including zero) are represented by a sign bit of 0 and a binary representation of the value   (b) negative values are represented by a sign bit of 1 and a binary representation of one less than the magnitude of the value.   
     
     
         2 . A microprocessor as claimed in  claim 1  wherein some or all bits of said immediate values are inverted or permuted. 
     
     
         3 . A microprocessor arranged to process instructions at least some of which contain at least one immediate value which forms an operand of the function, said immediate value being represented in a format which achieves a greater power efficiency than two's complement when said instructions are processed; the microprocessor further comprising at least one arithmetic and logic unit (ALU) having an input arranged to receive either one of said immediate values or an alternative value from elsewhere. 
     
     
         4 . A microprocessor as claimed in  claim 3 , wherein said format is standard sign magnitude format. 
     
     
         5 . A microprocessor as claimed in  claim 3 , wherein said format is a Gray code. 
     
     
         6 . A microprocessor as claimed in  claim 3 , which further comprises a multiplexor having a first input adapted to receive said one of said immediate values and a second input adapted to receive said alternative value. 
     
     
         7 . A microprocessor as claimed in  claim 6 , wherein said ALU is arranged to perform at least addition and subtraction, and wherein a conversion circuit, for converting values from said variant sign-magnitude format to two's complement, is merged with said ALU in such a way that the merged circuit operates with an overhead of one AND gate and one exclusive-or gate. 
     
     
         8 . A microprocessor as claimed in  claim 7 , wherein said multiplexor is connected to said ALU by a circuit substantially the same as that shown in  FIG. 10 . 
     
     
         9 . A microprocessor as claimed in  claim 3  wherein some or all bits of said immediate values are inverted or permuted.