Devices, systems, and methods to synchronize simultaneous dma parallel processing of a single data stream by multiple devices

Abstract

Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.

1 . An electronic device, comprising:
 a plurality of pattern-recognition processors, wherein each of the plurality of pattern-recognition processors comprises a parallel direct memory access (PDMA) master/slave input adapted to place that processor into a master or a slave mode, and a PDMA cycle connection adapted to transmit a direct memory access cycle from that processor, when placed into a master mode, to each of the plurality of pattern-recognition processors placed into a slave mode concurrently.   
   
   
       2 . The electronic device of  claim 1 , wherein each of the plurality of pattern-recognition processors comprises a data input adapted to receive data to be processed, wherein the data may be received by the plurality of pattern-recognition processors concurrently. 
   
   
       3 . The electronic device of  claim 1 , wherein each of the plurality of pattern-recognition processors comprises a plurality of address inputs adapted to receive address signals adapted to specify functions to be performed by that processor. 
   
   
       4 . The electronic device of  claim 3 , wherein a function to be performed comprises processing a data stream concurrently with one or more of the other processors during a direct memory access cycle transmitted from the one of the plurality of pattern-recognition processors placed into a master mode. 
   
   
       5 . The electronic device of  claim 1 , wherein that processor comprises a PDMA read/write input adapted to place that processor into a parallel read or a parallel write mode, whereby a data stream may be written into or read out of each of the plurality of pattern-recognition processors concurrently. 
   
   
       6 . The electronic device of  claim 5 , wherein the data stream being written into or read out of each of the plurality of pattern-recognition processors concurrently is performed during a single direct memory access cycle. 
   
   
       7 . An electronic system for processing data in parallel comprising:
 a processing unit adapted to activate a direct memory access (DMA) master device; and   a plurality of processing circuits adapted to process a data stream concurrently and independently of the processor, wherein the plurality of processing circuits includes the DMA master device and one or more DMA slave devices adapted to concurrently respond to DMA bus cycles.   
   
   
       8 . The electronic system of  claim 7 , wherein each of the plurality of processing circuits is a data pattern-recognition processor adapted to search the data according to a search criteria. 
   
   
       9 . The electronic system of  claim 8 , wherein the search criteria comprises at least one sequence of data searched for by the data pattern-recognition processors during a single search cycle. 
   
   
       10 . The electronic system of  claim 9 , wherein the DMA master device is adapted to transmit a direct memory access cycle to the DMA slave devices to initiate concurrent processing of the data stream, wherein the direct memory access cycle corresponds to one or more single search cycles. 
   
   
       11 . The electronic system of  claim 10 , wherein the DMA master device is adapted to place each of the DMA slave devices into a parallel read or a parallel write mode. 
   
   
       12 . The electronic system of  claim 7 , wherein the DMA master device is adapted to notify the processing unit of the completion of the data stream processing. 
   
   
       13 . A method for processing data comprising:
 activating a direct memory access (DMA) master device adapted to control the synchronous processing of a stream of data amongst the DMA master device and one or more DMA slave devices;   receiving the stream of data at the DMA master device and the one or more DMA slave devices; and   synchronously processing the stream of data in the DMA master device and the one or more DMA slave devices.   
   
   
       14 . The method of  claim 13 , wherein synchronously processing the stream of data concurrently comprises searching the stream of data for at least one sequence of data specified by a search criteria. 
   
   
       15 . The method of  claim 13 , wherein the processing by the plurality of processing circuits is based on received address signals adapted to indicate a particular processing function. 
   
   
       16 . The method of  claim 15 , comprising transmitting the processed stream of data to a processing unit. 
   
   
       17 . A method of processing data, comprising:
 activating one of a plurality of processing circuits when a stream of data is to be processed singularly by the one of the plurality of processing circuits;   activating a plurality of processing circuits when the stream of data is to be processed in parallel by the plurality of processing circuits;   activating one of the plurality of processing circuits as a direct memory access (DMA) master device adapted to control the synchronous processing of the stream of data amongst the plurality of processing circuits if the plurality of processing circuits are activated;   receiving the stream of data at all activated processing circuits concurrently; and   concurrently processing the stream of data at all the activated processing circuits.   
   
   
       18 . The method of  claim 17 , wherein processing the stream of data concurrently comprises searching the stream of data for least one sequence of data. 
   
   
       19 . The method of  claim 18 , comprising transmitting the processed stream of data to a processing unit. 
   
   
       20 . The method of  claim 17 , wherein the DMA master device is adapted to control the synchronous processing of the stream of data by transmitting a direct memory access cycle to other ones of the plurality of processing circuits, wherein the direct memory access cycle corresponds to one or more single search cycles. 
   
   
       21 . The method of  claim 20 , wherein the single search cycle comprises a time allotted to the plurality of processing circuits to process one unit of data in the stream of data. 
   
   
       22 . An electronic device, comprising:
 a processing unit adapted to transfer processing of a data stream to a plurality of processing circuits; and   a plurality of processing circuits adapted to process the data stream concurrently and transmit the results to the processing unit, wherein the plurality of processing circuits includes a DMA master device and one or more DMA slave devices.   
   
   
       23 . The electronic system of  claim 22 , wherein the plurality of processing circuits are data pattern-recognition processors adapted to process one unit of data during a single search cycle according to a search criteria. 
   
   
       24 . The electronic system of  claim 23 , wherein the single search cycle corresponds to a parallel DMA cycle controlled from the DMA master device and responded to by one or more DMA slave devices. 
   
   
       25 . The method of  claim 23 , wherein the at least one sequence of data to be searched is set at the DMA master device and at the one or more DMA slave devices based on received address and data signals. 
   
   
       26 . An electronic device, comprising:
 a plurality of pattern-recognition processors, wherein each of the plurality of pattern-recognition processors comprises a parallel direct memory access (PDMA) master/slave input adapted to place that processor into a master or a slave mode, and a PDMA connection adapted to receive DMA bus cycles concurrently.