Network routing system for enhanced efficiency and monitoring capability

Abstract

According to an embodiment of the invention, a network device such as a router or switch provides efficient data packet handling capability. The network device includes one or more input ports for receiving data packets to be routed, as well as one or more output ports for transmitting data packets. The network device includes an integrated port controller integrated circuit for routing packets. The integrated circuit includes an interface circuit, a received packets circuit, a buffer manager circuit for receiving data packets from the received packets circuit and transmitting data packets in one or more buffers and reading data packets from the one or more buffers. The integrated circuit also includes a rate shaper counter for storing credit for a traffic class, so that the integrated circuit can support input and/or output rate shaping. The integrated circuit may be associated with an IRAM, a CAM, a parameter memory configured to hold routing and/or switching parameters, which may be implemented as a PRAM, and an aging RAM, which stores aging information. The aging information may be used by a CPU coupled to the integrated circuit via a system interface circuit to remove entries from the CAM and/or the PRAM when an age count exceeds an age limit threshold for the entries.

1 . A network device, comprising:
 a plurality of input ports each configured to receive incoming data packets;   a central processing unit; and   an integrated port controller integrated circuit, under control of the central processing unit, configured to route the incoming data packets as outgoing data packets; and   a plurality of output ports, configured to transmit the outgoing data packets.   
     
     
         2 . A network device, as in  claim 1 , wherein the integrated port controller integrated circuit comprises:
 a packet input circuit, configured to determine the destination of the data packets and to prepare associated header information for preparing outgoing data packets; and   a buffer manager circuit, configured to store and retrieve contents of the data packets and the header associated information into and out of a plurality of buffers; and   a packet output circuit, configured to assemble the outgoing data packets from the contents of the data packets and the associated header information.   
     
     
         3 . A network device, as in  claim 2 , wherein the integrated port controller integrated circuit includes a rate shaper. 
     
     
         4 . A network device as in  claim 1 , further comprising a second integrated port controller integrated circuit coupled to the first integrated controller integrated circuit and under control of the central processing unit, configured to route the incoming data packets as outgoing data packets. 
     
     
         5 . A network device as in  claim 4 , wherein the first and second integrated port controller integrated circuits are coupled through a cross-point switch. 
     
     
         6 . A network device as in  claim 4 , further comprising a back plane interface adapter coupling the first and second integrated port controller integrated circuits to a backplane of the network device. 
     
     
         7 . A network device as in  claim 1 , wherein the integrated circuit comprises an ASIC. 
     
     
         8 . A network device as in  claim 1 , wherein the integrated circuit comprises a field programmable gate array. 
     
     
         9 . A network device as in  claim 1 , selected from the group consisting of a router and a switch. 
     
     
         10 . A network device as in  claim 1 , wherein the input ports comprise one or more gigabit Ethernet ports. 
     
     
         11 . A network device as in  claim 1 , wherein the input ports comprise one or more 10/100 megabit Ethernet ports. 
     
     
         12 . A network device as in  claim 1 , wherein the input ports comprise one or more packet over SONET ports. 
     
     
         13 . A network device as in  claim 1 , wherein the input ports comprise one or more ATM ports. 
     
     
         14 . A network device as in  claim 1 , further comprising a memory providing buffers for data packets. 
     
     
         15 . A network device as in  claim 1 , further including a content addressable memory (CAM) coupled to the integrated circuit, said CAM storing processed data packet information. 
     
     
         16 . A network device as in  claim 1 , further comprising a system interface circuit coupling the central processing unit to the integrated circuit.