Semiconductor device

Abstract

A semiconductor device includes a semiconductor chip, an electrically insulating element separated from the semiconductor chip by a space, and encapsulation material disposed in the space. The semiconductor chip includes a first face having a contact, and the electrically insulating element defines at least one through-hole. The encapsulation material is disposed around the semiconductor chip and around the electrically insulating element. Electrically conducting material is deposited in the through-hole of the electrically insulating element and communicates with the contact.

1 . A semiconductor device comprising:
 a semiconductor chip including a first face comprising a contact;   an electrically insulating element separated from the semiconductor chip by a space, the electrically insulating element defining at least one through-hole;   encapsulation material disposed in the space and around the semiconductor chip and around the electrically insulating element; and   electrically conducting material deposited in the at least one through-hole of the electrically insulating element and communicating with the contact.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the encapsulation material comprises an encapsulation body formed of an electrically insulating material that is different from material of the electrically insulating element. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the encapsulation body comprises a first main face and a second main face opposite the first main face, the semiconductor device comprising a first metallized trace disposed on the first main face and a second metallized trace disposed on the second main face. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the electrically conducting material connects between the first metallized trace and the second metallized trace. 
     
     
         5 . The semiconductor device of  claim 4 , further comprising:
 a memory element connected to the second metallized trace and electrically communicating with the contact of the semiconductor chip through the electrically conducting material and the first metallized trace.   
     
     
         6 . The semiconductor device of  claim 1 , comprising multiple semiconductor chips and multiple electrically insulating elements separated from each of the multiple semiconductor chips. 
     
     
         7 . The semiconductor device of  claim 6 , wherein at least one of the multiple electrically insulating elements defines multiple through-holes, the electrically conducting material deposited in each of the multiple through-holes. 
     
     
         8 . A method of assembling a semiconductor device comprising:
 placing at least two semiconductor chips on a carrier;   placing at least two electrically insulating material elements on the carrier;   applying encapsulation material over the at least two semiconductor chips and the at least two electrically insulating material elements to form an encapsulation workpiece;   generating at least one through-hole through each of the electrically insulating material elements; and   filling the at least one through-holes with an electrically conducting material.   
     
     
         9 . The method of  claim 8 , wherein the at least two semiconductor chips have a main face comprising contact elements, the at least two semiconductor chips placed on the carrier with the contact elements facing the carrier. 
     
     
         10 . The method of  claim 8 , further comprising:
 removing encapsulation material by one of grinding and etching a backside of the workpiece preparatory to opening the electrically insulating material elements.   
     
     
         11 . The method of  claim 8 , wherein generating at least one through-hole comprises one of illuminating with a light source, laser drilling, mechanically drilling, and etching each of the electrically insulating material elements. 
     
     
         12 . The method of  claim 8 , further comprising:
 removing the carrier from the encapsulation workpiece.   
     
     
         13 . The method of  claim 8 , further comprising:
 applying a first electrically conducting layer over a first main face of the encapsulation workpiece.   
     
     
         14 . The method of  claim 13 , comprising connecting the first electrically conducting layer between the electrically conducting material in the through-holes and contact elements of the semiconductor chips. 
     
     
         15 . The method of  claim 13 , further comprising:
 applying external contact elements to the first electrically conducting layer.   
     
     
         16 . The method of  claim 13 , further comprising:
 applying a second electrically conducting layer connected over a second main face of the encapsulation workpiece opposite the first main face.   
     
     
         17 . The method of  claim 17 , comprising connecting the second electrically conducting layer to the electrically conducting material in the through-holes. 
     
     
         18 . A method of fabricating a semiconductor package comprising:
 placing semiconductor chips on a carrier;   spacing electrically insulating elements on the carrier away from the semiconductor chips;   applying encapsulation material over the semiconductor chips and around the electrically insulating elements to form an encapsulation workpiece; and   providing at least one electrical pathway through each of the electrically insulating elements to enable coupling an electronic device to the workpiece that communicates with at least one of the semiconductor chips.   
     
     
         19 . The method of  claim 18 , comprising generating at least one through-hole in each of the electrically insulating material elements and filling the through-hole with an electrically conducting material. 
     
     
         20 . The method of  claim 19 , comprising applying an electrically conducting layer over at least one main face of the encapsulation workpiece and in contact with the electrically conducting material. 
     
     
         21 . The method of  claim 20 , comprising applying a first electrically conducting layer over a first main face of the encapsulation workpiece and a second electrically conducting layer over a second main face of the encapsulation workpiece, the first and second electrically conducting layers in contact with the electrically conducting material. 
     
     
         22 . The method of  claim 21 , wherein the electronic device comprises a memory device connected to the second electrically conducting layer. 
     
     
         23 . A semiconductor package comprising:
 at least one semiconductor chip;   at least one element comprising a first electrically insulating material and defining at least one through-hole;   an encapsulation body having a first main face and a second main face opposite the first main face, the encapsulation body comprising a second electrically insulating material surrounding the at least one semiconductor chip and the at least one element;   a first electrically conducting layer disposed on the first main face;   a second electrically conducting layer disposed on the second main face; and   electrically conducting material disposed in the at least one through-hole connecting the first electrically conducting layer with the second electrically conducting layer.   
     
     
         24 . The semiconductor package of  claim 23 , wherein the second electrically insulating material is disposed over the at least one element. 
     
     
         25 . The semiconductor package of  claim 23 , further comprising:
 a memory package electrically connected to the second electrically conducting layer.