Semiconductor devices and semiconductor device manufacturing methods

Abstract

Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.

1 . A method of manufacturing a semiconductor device including a localized silicon on insulator (SOI) structure, the method comprising:
 forming one or more floating body patterns in a region of a bulk substrate;   dividing the region of the bulk substrate into a lower bulk substrate region and a floating body region by etching lower regions of the one or more floating body patterns; and   filling a region between the floating body region and the lower bulk substrate region with an insulating material.   
   
   
       2 . The method of  claim 1 , further comprising:
 forming a well in the bulk substrate,   wherein the bulk substrate is of a first conductive type, and   the well includes the region of the bulk substrate.   
   
   
       3 . The method of  claim 2 , further comprising:
 forming a second well of a second conductive type in the bulk substrate; and   forming a third well of the first conductive type in the second well,   wherein the forming of the well includes forming the well of the first conductive type in the second well.   
   
   
       4 . The method of  claim 3 , wherein the well and the third well are separated from each other. 
   
   
       5 . The method of  claim 3 , further comprising:
 forming a peripheral device including a region of the second well;   forming a second peripheral device including a region of the third well; and   forming a one-transistor (1-T) dynamic random access memory (DRAM) cell including the floating body region.   
   
   
       6 . The method of  claim 5 , wherein the peripheral device includes one of an n-channel metal-oxide semiconductor (NMOS) transistor and a p-channel metal-oxide semiconductor (PMOS) transistor. 
   
   
       7 . The method of  claim 2 , further comprising:
 forming a second well of a second conductive type in the bulk substrate; and   forming a third well of the first conductive type in the second well,   wherein the forming of the well includes forming the well of the second conductive type in the third well.   
   
   
       8 . The method of  claim 2 , further comprising:
 forming a plurality of insulating regions on end sidewalls of the one or more floating body patterns,   wherein the dividing of the region of the bulk substrate includes forming a mask on the one or more floating body patterns and exposing bottom surfaces of the one or more floating body patterns through the mask,   the etching of the lower regions of the one or more floating body patterns includes selectively etching the lower regions with an isotropic etchant that etches through the bottom surfaces, and   the mask etches at a slower rate than the one or more floating body patterns.   
   
   
       9 . The method of  claim 1 , further comprising:
 forming a plurality of wells in a second region of the bulk substrate,   wherein the bulk substrate is of a first conductive type.   
   
   
       10 . The method of  claim 9 , wherein the forming of the plurality of wells includes forming a first well of a second conductive type in the bulk substrate, and
 forming second and third wells of the first conductive type in the first well.   
   
   
       11 . The method of  claim 9 , wherein the forming of the plurality of wells includes forming a first well of a second conductive type in the bulk substrate,
 forming a second well of the first conductive type in the first well, and   forming a third well of the second conductive type in the second well.   
   
   
       12 . The method of  claim 9 , wherein the floating body region is separated from the plurality of wells. 
   
   
       13 . A semiconductor device including a localized silicon on insulator (SOI) structure, comprising:
 a substrate region of a first conductive type bulk substrate;   an insulating region in the substrate region; and   a floating body region on the insulating region and separated from the substrate region by the insulating region, the floating body region and the substrate region including materials having similar characteristics.   
   
   
       14 . The semiconductor device of  claim 13 , further comprising:
 a well in the first conductive type bulk substrate,   wherein the well includes the substrate region.   
   
   
       15 . The semiconductor device of  claim 14 , further comprising:
 a second well of a second conductive type;   a third well of the first conductive type in the second well,   wherein the well is of the first conductive type and in the second well, the well separated from the third well.   
   
   
       16 . The semiconductor device of  claim 14 , further comprising:
 a second well of a second conductive type; and   a third well of the first conductive type in the second well,   wherein the well is of the second conductive type and in the third well.   
   
   
       17 . The semiconductor device of  claim 13 , further comprising:
 a plurality of wells in a second substrate region.   
   
   
       18 . The semiconductor device of  claim 17 , wherein the plurality of wells include a first well of a second conductive type, and
 a second well of the first conductive type in the first well.   
   
   
       19 . The semiconductor device of  claim 17 , wherein the plurality of wells include a first well of a second conductive type,
 a second well of the first conductive type in the first well, and   a third well of the second conductive type in the second well.   
   
   
       20 . The semiconductor device of  claim 17 , wherein the floating body region is separated from the plurality of wells.