System and Method for Detecting and Recovering from Errors in an Instruction Stream of an Electronic Data Processing System

Abstract

A system and method are provided for detecting and recovering from errors in an Instruction Cache RAM and/or Operand Cache RAM of an electronic data processing system. In some cases, errors in the Instruction Cache RAM and/or Operand Cache RAM are detected and recovered from without any required interaction of an operating system of the data processing system. Thus, and in many cases, errors in the Instruction Cache RAM and/or Operand Cache RAM can be handled seamlessly and efficiently, without requiring a specialized operating system routine, or in some cases, a maintenance technician, to help diagnose and/or fix the error.

1 - 29 . (canceled) 
     
     
         30 . A computer-readable data product containing encoded data that when read represents programmable instruction that when executed within a computing system implements a method for operating a pipelined instruction processor having a number of pipelined stages, the method comprising:
 queuing one or more instructions;   identifying which, if any, of the one or more queued instructions have a parity error;   setting a parity error bit for those queued instructions that have been identified as having a parity error, wherein the parity error bit, when set, indicates that the corresponding queued instruction has a parity error;   selecting a selected one of the one or more instructions for execution;   after the selected instructions has been selected for execution, determining if the selected instruction has a parity error by determining if the selected instruction has a parity error bit that has been set by the setting step;   halting execution of the selected instruction if the determining step determines that the selected instruction has a parity error; and   executing the selected instruction if the selected instruction does not have a parity error.   
     
     
         31 . The computer-readable data product of  claim 30 , further comprising the step of issuing a parity error abort message if the selected instruction is determined to have a parity error. 
     
     
         32 . The computer-readable data product of  claim 31  further comprising the steps of:
 storing the one or more queued instructions in an instruction queue;   providing one or more of the queued instructions to the instruction queue from a first level cache;   providing one or more of the queued instructions to the first level cache from a second level cache; and   reloading the selected instruction from the second level cache to the first level cache if the selected instruction has a parity error.   
     
     
         33 . The computer-readable data product of  claim 32 , wherein the selected instruction is initially read from a first portion of the first level cache, and wherein the selected instruction is reloaded from the second level cache into a second portion of the first level cache. 
     
     
         34 . The computer-readable data product of  claim 33 , further comprising the step of marking the first portion of the first level cache. 
     
     
         35 . The computer-readable data product of  claim 34 , further comprising the step of degrading a marked portion of the first level cache if a subsequent instruction is read from the marked portion of the first level cache and is determined to have a parity error. 
     
     
         36 . The computer-readable data product of  claim 35 , further comprising the step of reporting how many and/or which portions of the first level cache have been degraded. 
     
     
         37 . The computer-readable data product of  claim 32 , wherein the identifying step identifies those instructions that have a parity error as they are read from the first level cache and provided to the instruction queue. 
     
     
         38 . The computer-readable data product of  claim 37 , wherein the parity error bit is stored along with those instructions that have a parity error in the instruction queue. 
     
     
         39 . The computer-readable data product of  claim 37 , wherein the number of pipelined stages includes a first pipeline stage, and wherein the first pipeline stage includes a storage location for storing the parity error bit provided by the instruction queue. 
     
     
         40 . The computer-readable data product of  claim 39 , further comprising the steps of checking the parity error bit in the storage location of the first pipeline stage, and issuing the parity error abort message if the selected instruction has a parity error. 
     
     
         41 . A computer-readable data product containing encoded data that when read represents programmable instruction that when executed within a computing system implements a method for operating a pipelined instruction processor having a number of pipelined stages, the method comprising:
 detecting a parity error in one or more instructions before the pipelined instruction processor actually calls the one or more instructions for execution by the pipelined stages of the instruction processor; and   deferring interruption of the pipelined instruction processor until the pipelined instruction processor actually calls for execution of an instruction that has a detected parity error.   
     
     
         42 . A computer-readable data product containing encoded data that when read represents programmable instruction that when executed within a computing system implements a method for operating a cache memory that has a number of memory locations, the method comprising:
 reading a data word from a selected memory location of the cache memory;   checking the data word for a parity error, and if a parity error is present:   checking to see if the selected memory location was previously marked a predetermined number of times as having previously provide a data word with a parity error, and if so, degrading the selected memory location to prevent the selected memory location from further use, and if not, marking the selected memory location; and   writing another copy of the data word to the cache memory.   
     
     
         43 . The computer-readable data product of  claim 42 , wherein the another copy of the data word is written to a different memory location in the cache memory than the selected memory location. 
     
     
         44 . A computer-readable data product containing encoded data that when read represents programmable instruction that when executed within a computing system implements a method for operating a cache memory that has a number of memory locations, the method comprising:
 reading a data word from a selected memory location of the cache memory;   checking the data word for a parity error, and if a parity error is present;   checking to see if the selected memory location was previously marked as having previously provide a data word with a parity error, and if so, degrading the selected memory location to prevent the selected memory location from further use, and if not, marking the selected memory location;   writing another copy of the data word to the cache memory;   counting the number of degrades for the cache memory; and   issuing an alert if the number of degrades for the cache memory exceeds a predetermined threshold.