Semiconductor-on-insulator (soi) devices using void spaces

Abstract

An SOI substrate is fabricated by providing a substrate having a sacrificial layer thereon, an active semiconductor layer on the sacrificial layer remote from the substrate and a supporting layer that extends along at least two sides of the active semiconductor layer and the sacrificial layer and onto the substrate, and that exposes at least one side of the sacrificial layer. At least some of the sacrificial layer is etched through the at least one side thereof that is exposed by the supporting layer to form a void space between the substrate and the active semiconductor layer, such that the active semiconductor layer is supported in spaced-apart relation from the substrate by the supporting layer. The void space may be at least partially filled with an insulator lining.

1 . A semiconductor device, comprising:
 a semiconductor substrate;   a first device isolation layer extending straight in a first direction on the semiconductor substrate;   a second device isolation layer extending straight in a second direction perpendicular to the first direction on the semiconductor substrate;   an active semiconductor layer spaced apart from the semiconductor substrate and extending upward a thickness from the semiconductor substrate in fin-type;   a void space defined by the first device isolation layer and the second device isolation layer in a substantially horizontal direction and defined by the semiconductor substrate and the active semiconductor layer in a substantially vertical direction;   a gate electrode extending in a second direction on the first device isolation and the active semiconductor layer, and in contact with the upper surface and both sides of the active semiconductor layer;   a channel at least on both sides of the active semiconductor layer; and   a source/drain within the active semiconductor layer at both sides of the gate electrode.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , further comprising:
 an insulating layer on a surface of the semiconductor substrate facing the active semiconductor layer and on a surface of the active semiconductor layer facing the semiconductor substrate.   
     
     
         3 . The semiconductor device as claimed in  claim 1 , further comprising:
 a gate oxidation layer between the active semiconductor layer and the gate electrode to cover the upper surface and both sides of the active semiconductor layer.   
     
     
         4 . The semiconductor device as claimed in  claim 1 , wherein the first device isolation layer comprises a number of isolation layers for defining the source/drain, and the second device isolation layer comprises a pair of supporting layers for preventing collapse of the active semiconductor layer. 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein the active semiconductor is rectangular shaped and a vertical thickness is less than a horizontal width. 
     
     
         6 . The semiconductor device as claimed in  claim 1 , wherein the first device isolation layer is in contact with the gate electrode. 
     
     
         7 . The semiconductor device as claimed in  claim 1 , wherein an upper level of the first device isolation layer is the same upper level of the void space. 
     
     
         8 . The semiconductor device as claimed in  claim 1 , wherein the gate electrode having a structure of a triple fin FET is provided where the channel is provided on the upper surface and both sides of the active semiconductor layer. 
     
     
         9 . The semiconductor device as claimed in  claim 1 , further comprising:
 a pad oxidation layer and a silicon nitride layer on the upper surface of the active semiconductor layer.   
     
     
         10 . The semiconductor device as claimed in  claim 9 , wherein the gate electrode having a structure of a dual fin FET structure is provided where the channel is provided on both sides of the active layer. 
     
     
         11 . A semiconductor device, comprising:
 a substrate;   a first device isolation layer extending in a first direction on the substrate;   a second device isolation layer extending in a second direction on the substrate;   an active layer spaced apart from the substrate and extending upward a thickness from the substrate in fin-type;   a void space defined by the first device isolation layer and the second device isolation layer in a substantially horizontal direction and defined by the substrate and the active layer in a substantially vertical direction;   a gate electrode extending in a second direction on the first device isolation and the active layer;   a channel at least on both sides of the active layer; and   a source/drain within the active layer at both sides of the gate electrode.   
     
     
         12 . The semiconductor device as claimed in  claim 11 , wherein the substrate is a Si substrate, and the active layer is a Si epitaxial layer. 
     
     
         13 . The semiconductor device as claimed in  claim 11 , wherein the second direction is substantially perpendicular to the first direction. 
     
     
         14 . The semiconductor device as claimed in  claim 11 , further comprising:
 an insulating layer on a surface of the semiconductor substrate facing the active semiconductor layer and on a surface of the active semiconductor layer facing the semiconductor substrate.   
     
     
         15 . The semiconductor device as claimed in  claim 11 , further comprising:
 a gate oxidation layer between the active semiconductor layer and the gate electrode to cover the upper surface and both sides of the active semiconductor layer.   
     
     
         16 . The semiconductor device as claimed in  claim 11 , wherein the first device isolation layer comprises a number of isolation layers for defining the source/drain, and the second device isolation layer comprises a pair of supporting layers for preventing collapse of the active semiconductor layer. 
     
     
         17 . The semiconductor device as claimed in  claim 16 , wherein each of the first and second device isolation layers is bar shaped. 
     
     
         18 . The semiconductor device as claimed in  claim 17 , wherein the first device isolation layers have both ends coupled to one side of the second device isolation layers. 
     
     
         19 . The semiconductor device as claimed in  claim 11 , wherein the gate electrode is in contact with the upper surface, and both sides of the active layer and the channel is on the upper surface and both sides of the active semiconductor layer. 
     
     
         20 . The semiconductor device as claimed in  claim 11 , wherein the first device isolation layer is in contact with the gate electrode, and an upper level of the first device isolation layer is the same upper level of the void space.