Method and system for providing low density parity check (ldpc) coding for scrambled coded multiple access (scma)

Abstract

A multiple access scheme is described. One or more encoders are configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding. The bit streams correspond to a respective plurality of terminals. The plurality of bit streams are converted to provide a multiple access scheme for the terminals.

1 . A method comprising:
 encoding a plurality of bit streams using Low Density Parity Check (LDPC) coding, wherein the bit streams correspond to a respective plurality of terminals; and   converting the plurality of bit streams to provide a multiple access scheme for the terminals.   
     
     
         2 . A method according to  claim 1 , wherein the converting the plurality of bit streams further comprises:
 scrambling the bit streams using a plurality of respective scrambling signatures, wherein the bit streams include a first bit stream associated with a first terminal and a second terminal associated with a second terminal,   wherein the scrambling signatures include a first scrambling signature assigned to the first terminal, and a second scrambling signature assigned to the second terminal.   
     
     
         3 . A method according to  claim 2 , further comprising:
 spreading the scrambled bit streams to match a communication channel bandwidth.   
     
     
         4 . A method according to  claim 2 , wherein the encoding comprises:
 accessing memory storing information representing a structured parity check matrix of the LDPC codes, the information being organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix, the rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation; and   outputting an LDPC coded signal based on the stored information representing the parity check matrix.   
     
     
         5 . A method according to  claim 4 , wherein the parity bits are determined sequentially, the method further comprising:
 determining an 0 th  parity bit by adding any j th  information bit if the j th  entry in the 0 th  row of the parity check matrix is 1; and   determining an i th  parity bit by adding the (i−1) th  parity bit and any j th  information bit if the j th  entry in the i th  row of the parity check matrix is 1, wherein i>0.   
     
     
         6 . A method according to  claim 4 , further comprising:
 initializing parity bit accumulators to zero;   accumulating the first information bit in the j th  group of M information bits in the i th  parity bit accumulator if the i th  entry in (jM) th  column of the parity check matrix is 1, where j=0,1,2,3, . . . k ldpc /M−1;   accumulating the remaining (M−1) information bits m=jM+1, jM+2, jM+3, . . . , (j+1)M−1 of the j th  group in the parity bit accumulators whose addresses are given by {x+m mod M×q}mod(n ldpc −k ldpc ), wherein x denotes the address of the parity bit accumulator corresponding to the first bit, jM, in the group, and q is a code rate dependent constant; and   after all of the information bits are exhausted, performing operations, starting with i=1 according to p i =p i ⊕p i−1 , i=1,2, . . . , n ldpc −k ldpc −1, wherein final content of p i , i=0,1, . . . , n ldpc −k ldpc −1 is equal to the parity bit p i .   
     
     
         7 . A method according to  claim 6 , wherein M is 50 and 100 and the code dependent constant q is 64 and 56 for code rates 1/9 and 1/15, respectively. 
     
     
         8 . A method according to  claim 4 , wherein the row indices of 1's in the column index j*M 
       
         
           
             
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       of the parity check matrix are given at the j th  row according to one of Tables 1 and 2: 
       
         
           
                 
               
                   TABLE 1 
                 
                     
                 
                   Address of Parity Bit Accumulators (Rate 1/9) 
                 
                     
                 
                     
                 
                 
                 
               
                     
                   0 1380 2744 
                 
                     
                   1 332 2984 
                 
                     
                   2 2784 2624 
                 
                     
                   3 92 596 
                 
                     
                   4 180 1160 
                 
                     
                   5 464 1624 
                 
                     
                   6 2556 1580 
                 
                     
                   7 708 1008 
                 
                     
                     
                 
             
                
                
                
                
               
               
                
               
            
             
                
                
                
                
                
                
                
                
                
               
            
           
         
         
           
                 
               
                   TABLE 2 
                 
                     
                 
                   Address of Parity Bit Accumulators (Rate 1/15) 
                 
                     
                 
                     
                 
                 
                 
               
                     
                   0 4788 4536 
                 
                     
                   1 2849 2282 
                 
                     
                   2 1750 2947 
                 
                     
                   3 1197 4151 
                 
                     
                     
                 
             
                
                
                
                
               
               
                
               
            
             
                
                
                
                
                
               
            
           
         
       
       wherein k ldpc  is associated with a length of the bit streams. 
     
     
         9 . A method according to  claim 8 , wherein the row indices of 1's in other column indices m (m modulo M≠0 and m<k ldpc ) of the parity check matrix are given by {x+m mod M×q}mod(n ldpc −k ldpc ), wherein x denotes an entry at the j th  row of Tables 1-2, where j=int{m/M}, and int{.} denotes the integer function, the row indices of 1's in the column index m=k ldpc +j (j=0,1,2, . . . , n ldpc −k ldpc −2) of the parity check matrix being given by j and j+1, the row index of 1 in the column index n ldpc −1 of the parity check matrix being given by n ldpc −k ldpc −1. 
     
     
         10 . A method according to  claim 9 , wherein q=64 and M=50 for rate 1/9 LDPC code and q=56 and M=100 for rate 1/15 LDPC code. 
     
     
         11 . A method according to  claim 1 , wherein the scrambling signatures include Gold sequences. 
     
     
         12 . An apparatus comprising:
 one or more encoders configured to encode a plurality of bit streams using Low Density Parity Check (LDPC) coding; and;   one or more scramblers configured to scramble the bit streams using a plurality of respective scrambling signatures to provide a multiple access scheme, wherein the bit streams include a first bit stream associated with a first terminal and a second terminal associated with a second terminal,   wherein the scrambling signatures include a first scrambling signature assigned to the first terminal, and a second scrambling signature assigned to the second terminal.   
     
     
         13 . An apparatus according to  claim 12 , further comprising:
 one or more spreaders configured to spread the scrambled bit streams to match a communication channel bandwidth.   
     
     
         14 . An apparatus according to  claim 12 , further comprising:
 memory configured to store information representing a structured parity check matrix of the LDPC codes, the information being organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix, the rows correspond to groups of columns of the parity check matrix,   wherein subsequent columns within each of the groups are derived according to a predetermined operation,   wherein the stored information representing the parity check matrix is retrieved and used to output an LDPC coded signal.   
     
     
         15 . An apparatus according to  claim 14 , wherein an 0 th  panty bit is determined by adding any j th  information bit if the j th  entry in the 0 th  row of the parity check matrix is 1 and an i th  parity bit is determined by adding the (i−1) th  parity bit and any j th  information bit if the j th  entry in the i th  row of the parity check matrix is 1, wherein i>0. 
     
     
         16 . An apparatus according to  claim 14 , wherein parity bit accumulators are initialized to zero, the first information bit in the j th  group of M information bits is accumulated in the i th  parity bit accumulator if the i th  entry in (jM) th  column of the parity check matrix is 1, where j=0,1,2,3, . . . k ldpc /M−1, the remaining (M−1) information bits m=jM+1, jM+2, jM+3, . . . , (j+1)M−1 of the j th  group being accumulated in the parity bit accumulators whose addresses are given by {x+m mod M×q}mod(n ldpc −k ldpc ), wherein x denotes the address of the parity bit accumulator corresponding to the first bit, jM, in the group, and q is a code rate dependent constant, and after all of the information bits are exhausted, operations, starting with i=1 are performed according to p i=p   i ⊕p i−1 , i=1, 2, . . . , n ldpc −k ldpc −1, wherein final content of p i , i=0,1, . . . , n ldpc −k ldpc −1 is equal to the parity bit p i . 
     
     
         17 . An apparatus according to  claim 14 , wherein M is 50 and 100 and the code dependent constant q is 64 and 56 for code rates 1/9 and 1/15, respectively. 
     
     
         18 . An apparatus according to  claim 12 , wherein the scrambling signatures include Gold sequences. 
     
     
         19 . A method comprising:
 applying joint detection and interference cancellation on a received composite signal, wherein the composite signal includes one or more encoded bit streams having a low code rate;   estimating the encoded bit streams;   converting the estimated bit streams;   decoding the converted bit streams;   modifying the composite signal based on the decoded bit stream; and   iteratively decoding bit streams of the modified composite signal.   
     
     
         20 . A method according to  claim 19 , wherein the received composite signal includes one or more pilot signals for synchronization, the method further comprising:
 performing synchronization based on the pilot signals.   
     
     
         21 . A method according to  claim 19 , wherein the decoding is based on a Low Density Parity Check (LDPC) code and comprises:
 initializing a plurality of log likelihood associated with the descrambled bit streams;   updating a value of a check node based on values of the plurality of log likelihood;   updating a value of a bit node based on one or more check node associated with the bit node; and   outputting the decoded bit stream.   
     
     
         22 . A method according to  claim 21 , further comprising:
 determining whether a parity check equation is satisfied; and   repeating the updating a value of a check node and the updating a value of a bit node if the parity check equation is not satisfied.   
     
     
         23 . A method according to  claim 19 , wherein the low code rate includes rate 1/9 or rate 1/15. 
     
     
         24 . A method according to  claim 19 , wherein the converting the estimated bit streams comprises:
 descrambling the estimated bit streams.   
     
     
         25 . A method according to  claim 21 , wherein scrambling signatures include Gold sequences.