1-transistor type dram cell, a dram device and manufacturing method therefore, driving circuit for dram, and driving method therefor

Abstract

The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line and the bottom word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process biasing the word line and the bottom word line at the second constant voltage level and supplying a write data to the bit line.

1 . A driving circuit of an 1-transistor type DRAM having a double data structure comprising:
 a transistor storing data on a floating body;   a word line formed on the upper side of the transistor and controlling the transistor;   a bottom word line formed on the lower side of the transistor and controlling the transistor;   a sensing line connected to the floating body of the transistor;   a bit line connected to the floating body; a bit line connected to the floating body;   a sense amp sensing data on the bit line to distinguish multi-level data; and   a write driver connected to the sense amp and supplying a plurality of driving voltages to the sense amp.   
   
   
       2 . The method as set forth in  claim 1 , wherein the multi-level data is data with different levels driven using a 4-level current. 
   
   
       3 . The method as set forth in  claim 1 , wherein the plurality of driving voltages is generated using a plurality of reference voltages.