US2010117451A1PendingUtilityA1
Package circuit board with a reduced number of pins and package including a package circuit board with a reduced number of pins and methods of manufacturing the same
Est. expiryJan 7, 2024(expired)· nominal 20-yr term from priority
H10W 74/00H10W 90/28H10W 72/823H10W 72/884H10W 72/5449H10W 72/07554H10W 90/754H10W 72/9445H10W 72/952H10W 72/90H10W 72/922H10W 70/655H10W 90/00H10W 90/724H10W 90/722H10W 72/244H10W 90/734H10W 74/117H10W 72/00H10W 70/657H10W 44/20H10W 90/701H10W 72/071
43
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.
Claims
exact text as granted — not AI-modified1 . A method of reducing a number of input/output (I/O) ports on a semiconductor substrate, comprising:
receiving a first voltage at a semiconductor substrate, the first voltage being the only power supply voltage received by the semiconductor substrate; converting the first voltage into at least one other power supply voltage; and supplying the at least one other supply voltage to a microelectronic chip.
2 . A method of forming a package circuit board, comprising:
forming a semiconductor integrated circuit on a first surface of a semiconductor substrate, the semiconductor integrated circuit configured to process at least one signal associated with a microelectronic chip; and forming a plurality of signal input/output (I/O) ports on a second surface of the semiconductor substrate, the second surface not including the first surface, at least a portion of the second surface being electrically connected to the semiconductor integrated substrate.
3 . A method of fabricating a package circuit board, comprising:
patterning an integrated circuit on a first surface of a substrate, the integrated circuit including at least one passive element that includes at least one of a capacitor, an inductor, a resistor, and a pass filter; forming a plurality of signal input/output (I/O) ports on a second surface of the substrate, the second surface not including the first surface, at least a portion of the second surface being electrically connected to the integrated circuit; and mounting a microelectronic chip on the integrated circuit, wherein the integrated circuit is configured to process at least one signal associated with the microelectronic chip.
4 . A method of fabricating a package circuit board comprising:
forming a plurality of input/output (I/O) ports including a plurality of power supply pins on one side of a substrate, the substrate being configured to receive a single power supply voltage from the plurality of power supply pins and to convert the single power supply voltage into at least one other power supply voltage; and mounting a microelectronic chip on a portion of the substrate, the microelectronic chip including at least one device requiring the at least one other power supply voltage, wherein the substrate includes a voltage converter for converting the single power supply voltage into the at least one other required power supply voltage.Join the waitlist — get patent alerts
Track US2010117451A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.