Transistor for Preventing or Reducing Short Channel Effect and Method for Manufacturing the Same

Abstract

A transistor for preventing or reducing short channel effect includes a substrate; a gate stack disposed over the substrate; a first junction region disposed on the substrate at a first side surface of the gate stack, said first junction layer being formed of an epitaxial layer; a trench formed within the substrate at a second side surface of the gate stack; and a second junction region disposed below the trench, said second junction layer being lower than the first junction region.

1 . A transistor for preventing or reducing short channel effect, comprising:
 a substrate;   a gate stack disposed over the substrate;   a first junction region disposed on the substrate at a first side surface of the gate stack, said junction layer formed of an epitaxial layer;   a trench formed within the substrate at a second side surface of the gate stack; and   a second junction region disposed below the trench, said junction being lower than the first junction region.   
   
   
       2 . The transistor for preventing or reducing short channel effect of  claim 1 , further comprising
 a first contact plug in contact with the first junction region; and   a second contact plug filling the trench and in contact with the second junction region.   
   
   
       3 . The transistor for preventing or reducing short channel effect of  claim 1 , wherein the substrate comprises a trench formed within the substrate at the first side surface of the gate stack, and the first junction region is formed of an epitaxial layer filling the trench. 
   
   
       4 . The transistor for preventing or reducing short channel effect of  claim 1 , wherein in a cell region, the first junction region comprises a drain region to be connected to a capacitor. 
   
   
       5 . The transistor for preventing or reducing short channel effect of  claim 1 , wherein in a peripheral circuit region, the first junction region comprises a drain region to which a drain-source voltage V ds  is to be applied. 
   
   
       6 . The transistor for preventing or reducing short channel effect of  claim 1 , wherein the epitaxial layer is formed of a doped epitaxial layer. 
   
   
       7 . The transistor for preventing or reducing short channel effect of  claim 6 , wherein the doped epitaxial layer comprises an impurity region into which N-type or P-type impurities are implanted. 
   
   
       8 . The transistor for preventing or reducing short channel effect of  claim 1 , wherein the gate stack fills a recess trench comprising a first side wall formed within the semiconductor substrate in a vertical direction and a second side wall having a predetermined angle with respect to the surface of the semiconductor substrate and a vertical end, which is in contact with a vertical end of the first side wall. 
   
   
       9 . A method for manufacturing a transistor for preventing or reducing short channel effect, comprising:
 forming a gate stack over a substrate;   exposing a side surface of the gate stack and a first portion of the substrate;   forming a first trench by etching the exposed first portion of the substrate;   forming a first junction region by filling the first trench with an epitaxial layer;   exposing the other side surface of the gate stack and a second portion of the substrate while blocking the first junction region;   forming a second trench which is deeper than the first trench by etching the exposed second portion of the substrate; and   forming a second junction region within the substrate below the second trench by performing an ion implantation process on the exposed second trench.   
   
   
       10 . The method of  claim 9 , wherein forming the gate stack comprises:
 forming a recess trench including a first side wall formed within the semiconductor substrate in a vertical direction and a second side wall having a predetermined angle with respect to the surface of the semiconductor substrate;   forming the gate stack so as to be aligned with the recess trench; and   forming a spacer on the side wall of the gate stack.   
   
   
       11 . The method of  claim 9 , comprising forming the epitaxial layer by Selective Epitaxial Growth (SEG). 
   
   
       12 . The method of  claim 9 , wherein in a cell region, the first junction region comprises a drain region to be connected to a capacitor. 
   
   
       13 . The method of  claim 9 , wherein in a peripheral circuit region, the first junction region comprises a drain region to which a drain-source voltage V ds  is to be applied. 
   
   
       14 . The method of  claim 9 , wherein forming the first junction region comprises:
 forming the epitaxial layer as an undoped Selective Epitaxial Growth (SEG) layer;   implanting N-type conductive impurities into the epitaxial layer; and   annealing the epitaxial layer thereby forming the first junction region.   
   
   
       15 . The method of  claim 9 , wherein forming the first junction region comprises:
 forming the epitaxial layer as an undoped Selective Epitaxial Growth (SEG) layer;   implanting N-type or P-type conductive impurities into the epitaxial layer; and   annealing the epitaxial layer thereby forming the first junction region.   
   
   
       16 . The method of  claim 9 , wherein forming the first junction region comprises:
 forming the epitaxial layer as an doped Selective Epitaxial Growth (SEG) layer; and   annealing the epitaxial layer thereby forming the first junction region.