Vertical IGBT Device

Abstract

According to one embodiment, a power semiconductor device comprises a semiconductor substrate. A transistor gate structure is arranged in a trench formed in the semiconductor substrate. A body region of a first conductivity type is arranged adjacent the transistor gate structure and a first highly-doped region of a second conductivity type is arranged in an upper portion of the body region. A drift zone of the second conductivity type is arranged below the body region and a second highly-doped region of the second conductivity type is arranged below the drift zone. An end-of-range irradiation region is arranged adjacent the transistor gate structure and has a plurality of vacancies. In some embodiments, at least some of the vacancies are occupied by metals.

1 . A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure, comprising:
 forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate;   forming a body region between adjacent ones of the transistor gate structures; and   forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.   
     
     
         2 . The method of  claim 1 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises forming the end-of-range irradiation region in the body region between adjacent ones of the transistor gate structures. 
     
     
         3 . The method of  claim 1 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises forming the end-of-range irradiation region below the body region between adjacent ones of the transistor gate structures. 
     
     
         4 . The method of  claim 1 , further comprising forming an insulating layer on the semiconductor substrate before the end-of-range irradiation region is formed. 
     
     
         5 . The method of  claim 4 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises:
 forming an opening in the insulating layer in a region of the insulating layer arranged over the body region; and   irradiating the semiconductor substrate through the opening formed in the insulating layer.   
     
     
         6 . The method of  claim 5 , further comprising forming a resist layer on the insulating layer before the opening is formed in the insulating layer. 
     
     
         7 . The method of  claim 6 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises irradiating the semiconductor substrate through the resist layer and the opening formed in the insulating layer. 
     
     
         8 . The method of  claim 6 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises:
 forming an opening in the resist layer in a region of the opening formed in the insulating layer; and   irradiating the semiconductor substrate through the openings formed in the resist and insulating layers.   
     
     
         9 . The method of  claim 1 , further comprising occupying at least some of the vacancies in the end-of-range irradiation region with metals. 
     
     
         10 . The method of  claim 9 , wherein occupying at least some of the vacancies in the end-of-range irradiation region with metals comprises:
 diffusing the metals into the semiconductor substrate; and   annealing the semiconductor substrate at a relatively high temperature.   
     
     
         11 . The method of  claim 10 , wherein diffusing the metals into the semiconductor substrate comprises:
 forming a metal silicide layer on the semiconductor substrate or implanting metal into the semiconductor substrate; and   heating the semiconductor substrate.   
     
     
         12 . The method of  claim 11 , wherein the semiconductor substrate is heated to a temperature ranging between approximately 600° and 800° C. for a duration ranging between approximately 30 minutes and 120 minutes. 
     
     
         13 . The method of  claim 10 , wherein the metals are diffused into the semiconductor substrate before the end-of-range irradiation region is formed. 
     
     
         14 . The method of  claim 13 , wherein the metals are diffused into the semiconductor substrate before the end-of-range irradiation region is formed at a temperature ranging between approximately 700° and 900° C. for a duration ranging between approximately 30 minutes and 120 minutes. 
     
     
         15 . A reduced free-charge carrier lifetime semiconductor structure, comprising:
 a plurality of transistor gate structures arranged in trenches formed in a semiconductor substrate;   a body region arranged between adjacent ones of the transistor gate structures; and   an end-of-range irradiation region arranged between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.   
     
     
         16 . The reduced free-charge carrier lifetime semiconductor structure of  claim 15 , wherein at least some of the vacancies in the end-of-range irradiation region are occupied by metals. 
     
     
         17 . The reduced free-charge carrier lifetime semiconductor structure of  claim 16 , wherein the metals comprise palladium or platinum. 
     
     
         18 . The reduced free-charge carrier lifetime semiconductor structure of  claim 15 , wherein the end-of-range irradiation region is arranged in the body region between adjacent ones of the transistor gate structures. 
     
     
         19 . The reduced free-charge carrier lifetime semiconductor structure of  claim 15 , wherein the end-of-range irradiation region is arranged below the body region between adjacent ones of the transistor gate structures. 
     
     
         20 . A method of manufacturing a power semiconductor device, comprising:
 providing a semiconductor substrate;   forming a transistor gate structure in a trench arranged in the semiconductor substrate;   forming a body region of a first conductivity type adjacent the transistor gate structure;   forming a first highly-doped region of a second conductivity type in an upper portion of the body region;   forming a drift zone of the second conductivity type below the body region;   forming a second highly-doped region of the second conductivity type below the drift zone; and   forming an end-of-range irradiation region adjacent the transistor gate structure, the end-of-range irradiation region having a plurality of vacancies.   
     
     
         21 . The method of  claim 20 , wherein forming the end-of-range irradiation region adjacent the transistor gate structure comprises forming the end-of-range irradiation region in the body region adjacent the transistor gate structure. 
     
     
         22 . The method of  claim 20 , wherein forming the end-of-range irradiation region adjacent the transistor gate structure comprises forming the end-of-range irradiation region below the body region in the drift zone adjacent the transistor gate structure. 
     
     
         23 . The method of  claim 20 , further comprising occupying at least some of the vacancies in the end-of-range irradiation region with metals. 
     
     
         24 . A power semiconductor device, comprising:
 a semiconductor substrate;   a transistor gate structure arranged in a trench formed in the semiconductor substrate;   a body region of a first conductivity type arranged adjacent the transistor gate structure;   a first highly-doped region of a second conductivity type arranged in an upper portion of the body region;   a drift zone of the second conductivity type arranged below the body region;   a second highly-doped region of the second conductivity type arranged below the drift zone; and   an end-of-range irradiation region arranged adjacent the transistor gate structure, the end-of-range irradiation region having a plurality of vacancies.   
     
     
         25 . The power semiconductor device of  claim 24 , wherein at least some of the vacancies in the end-of-range irradiation region are occupied by metals. 
     
     
         26 . The power semiconductor device of  claim 25 , wherein the metals comprise palladium or platinum. 
     
     
         27 . The power semiconductor device of  claim 24 , wherein the end-of-range irradiation region is arranged in the body region adjacent the transistor gate structure. 
     
     
         28 . The power semiconductor device of  claim 24 , wherein the end-of-range irradiation region is arranged below the body region in the drift zone adjacent the transistor gate structure. 
     
     
         29 . A power semiconductor device, comprising:
 a semiconductor substrate;   a plurality of transistor gate structures arranged in trenches formed in the semiconductor substrate;   a body region of a first conductivity type arranged between adjacent ones of the transistor gate structures;   a first highly-doped region of a second conductivity type arranged in an upper portion of the body regions;   a drift zone of the second conductivity type arranged below the body regions;   a contact region having a first doped region of the first conductivity type arranged below the drift zone under some of the transistor gate structures and a second doped region of the second conductivity type arranged below the drift zone under the other transistor gate structures; and   an end-of-range irradiation region having a plurality of vacancies arranged between adjacent ones of the transistor gate structures disposed above the second doped region of the contact region, but not between adjacent ones of the transistor gate structures disposed above the first doped region of the contact region.   
     
     
         30 . The power semiconductor device of  claim 29 , wherein the end-of-range irradiation region is arranged in the body region adjacent the transistor gate structure. 
     
     
         31 . The power semiconductor device of  claim 29 , wherein the end-of-range irradiation region is arranged below the body region in the drift zone adjacent the transistor gate structure.