Layout verification apparatus, layout apparatus, layout verification method, layout verification program, and wiring forming method

Abstract

The layout verification apparatus includes: a verification unit for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and a correction hint creating unit for creating correction hint information based on the error part, and for sending the correction hint information to a layout and wiring unit for correcting the layout and wiring data. The correction hint creating unit obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring unit.

1 . A layout verification apparatus, comprising:
 verification means for obtaining mask data indicating a mask pattern to be drawn on a mask based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and for verifying a position of the mask pattern based on the mask data, so as to detect an error part; and   correction hint creating means for creating correction hint information based on the error part, and for sending the correction hint information to layout and wiring means for correcting the layout and wiring data,   wherein the correction hint creating means obtains terminal information indicating positions of a group of terminals included in the group of primitive cells and creates the correction hint information based on the terminal information so that the positions of the group of terminals are not changed by the layout and wiring means.   
     
     
         2 . A layout verification apparatus according to  claim 1 , wherein the verification means includes:
 lithography simulation means for simulating a wiring shape that is formed after a lithography step is performed based on the mask data, so as to create post-lithography graphic data; and   error detection means for detecting the error part based on the post-lithography graphic data.   
     
     
         3 . A layout verification apparatus according to claim  2 , wherein:
 the verification means further includes optical proximity correction (OPC) means for performing an OPC process on the mask data so as to create post-OPC graphic data; and   the lithography simulation means creates the post-lithography graphic data based on the post-OPC graphic data.   
     
     
         4 . A layout verification apparatus according to  claim 2 , wherein the correction hint creating means recognizes a group of patterns corresponding to the connection wires and a group of patterns corresponding to the group of terminals as a group of wiring patterns and a group of terminal patterns, respectively, in the post-simulation data based on the terminal information. 
     
     
         5 . A layout verification apparatus according to  claim 4 , wherein if the error part is detected between a first wiring pattern and a second wiring pattern, and if a space L 1  formed between the first wiring pattern and a wiring pattern, which is adjacent to the first wiring pattern and is not the second wiring pattern, is larger than a space L 2  formed between the second wiring pattern and a wiring pattern, which is adjacent to the second wiring pattern and is not the first wiring pattern, the correction hint creating means creates the correction hint information so that a position of a part corresponding to the first wiring pattern is changed in the layout and wiring data. 
     
     
         6 . A layout verification apparatus according to  claim 4 , wherein if the error part is detected between a first terminal pattern and a third wiring pattern, the correction hint creating means creates the correction hint information so that a position of a part corresponding to the third wiring pattern is changed in the layout and wiring data. 
     
     
         7 . A layout verification apparatus according to  claim 1 , wherein if the error part is detected between a third terminal pattern and a fourth terminal pattern, the correction hint creating means recognizes a wiring pattern that is connected to one of the third terminal pattern and the fourth terminal pattern as the fourth wiring pattern, and creates the correction hint information so that a position of a part corresponding to the fourth wiring pattern is changed in the layout and wiring data. 
     
     
         8 . A layout verification apparatus according to claim  21 , wherein if the error part is detected between a fourth terminal pattern and a fifth terminal pattern, the correction hint creating means recognizes a wiring pattern that is adjacent to the fourth terminal pattern as a fourth neighboring pattern, recognizes a wiring pattern that is adjacent to the fifth terminal pattern as a fifth neighboring pattern, determines any one of the fourth neighboring pattern and the fifth neighboring pattern as an alteration wiring pattern, and creates the correction hint information so that a position of a part corresponding to the alteration wiring pattern is changed in the layout and wiring data. 
     
     
         9 . A layout verification apparatus according to  claim 8 , wherein the correction hint creating means determines the alteration wiring pattern based on a line width W 4  of the fourth neighboring pattern and a line width W 5  of the fifth neighboring pattern. 
     
     
         10 . A layout verification apparatus according to  claim 8 , wherein the correction hint creating means determines the alteration wiring pattern based on a space SP 1 - 1  formed between the fourth neighboring pattern and the fourth terminal pattern and a space SP 1 - 2  formed between the fifth neighboring pattern and the fifth terminal pattern. 
     
     
         11 . A layout verification apparatus according to  claim 8 , wherein the correction hint creating means recognizes a wiring pattern, which is adjacent to the fourth neighboring pattern and is not the fourth terminal pattern, as a fourth pattern, recognizes a wiring pattern, which is adjacent to the fifth neighboring pattern and is not the fifth terminal pattern, as a fifth pattern, and determines the alteration wiring pattern based on a space SP 2 - 1  formed between the fourth neighboring pattern and the fourth pattern and a space SP 2 - 2  formed between the fifth neighboring pattern and the fifth pattern. 
     
     
         12 . A layout apparatus, comprising:
 the layout verification apparatus according to  claim 1 ; and   layout and wiring means for correcting positions of the connection wires in the layout and wiring data based on the correction hint information, so as to output the corrected data as wiring layout data.   
     
     
         13 . A layout verification method, comprising:
 obtaining, by a computer, mask data indicating positions of mask regions that are masked when wirings are formed based on layout and wiring data indicating positions of a group of primitive cells and positions of connection wires connected to the group of primitive cells, and verifying the positions of the mask regions based on the mask data, so as to detect an error part;   creating, by the computer, correction hint information based on the error part; and   sending, by the computer, the correction hint information to layout and wiring means for correcting the layout and wiring data,   wherein the creating the correction hint information includes creating the correction hint information based on terminal information indicating positions of a group of terminals included in the group of primitive cells so that the positions of the group of terminals are not changed by the layout and wiring means.   
     
     
         14 . A layout verification program for realizing, by using a computer, the layout verification method according to  claim 13 . 
     
     
         15 . A wiring forming method, comprising:
 correcting, by using a computer, position of connection wires in layout and wiring data based on correction hint information that is sent by the layout verification method according to  claim 13 , so as to create wiring layout data;   manufacturing a mask based on the wiring layout data; and   forming wirings by using the mask.