Photomask quality estimation system and method for use in manufacturing of semiconductor device, and method for manufacturing the semiconductor device

Abstract

A photomask quality estimation system comprises a measuring unit, a latitude computation unit and an estimation unit. The measuring unit measures the mask characteristic of each of a plurality of chip patterns formed on a mask substrate. The latitude computation unit computes the exposure latitude of each chip pattern based on the mask characteristic. The estimation unit estimates the quality of each chip pattern based on the exposure latitude.

1 .- 20 . (canceled) 
   
   
       21 . A method for manufacturing a semiconductor device, comprising:
 preparing a photomask, wherein
 the photomask includes a plurality of chip patterns formed on a mask substrate, the plurality of chip patterns including identical chip patterns for forming the semiconductor device, 
 a mask characteristic of each of the plurality of chip patterns is measured, 
 an exposure latitude of said each chip pattern is computed based on the mask characteristic, and 
 quality of said each chip pattern is estimated based on the exposure latitude, the estimating the quality including comparing the exposure latitude of said each chip pattern with an upper limit set for the exposure latitude of the entire mask substrate, and determining whether the exposure latitude of said each chip pattern is equal to or less than the upper limit; and 
 forming a pattern on a substrate using said each chip pattern formed on the mask substrate that satisfies the determination. 
   
   
   
       22 . The method for manufacturing a semiconductor device according to  claim 21 , wherein the forming the pattern includes projecting image of said each chip pattern onto a resist film coated on the substrate to form a resist pattern on the substrate; and
 the method further comprises forming a circuit pattern corresponding to said each chip pattern on the substrate, using the resist pattern as a mask.   
   
   
       23 . The method for manufacturing a semiconductor device according to  claim 21 , wherein the determining whether the exposure latitude of said each chip pattern is equal to or less than the upper limit determines that the quality of said each chip pattern is acceptable when the exposure latitude of said each chip pattern is equal to or less than the upper limit, and determines that the quality of said each chip pattern is unacceptable when the exposure latitude of said each chip pattern is more than the upper limit. 
   
   
       24 . The method for manufacturing a semiconductor device according to  claim 22 , further comprising computing trimming values of a plurality of fuses included in the circuit pattern based on the mask characteristic of said each chip pattern. 
   
   
       25 . The method for manufacturing a semiconductor device according to  claim 24 , further comprising melting and cutting part of the fuses based on the trimming values to unify the circuit pattern in electrical characteristic. 
   
   
       26 . The method for manufacturing a semiconductor device according to  claim 21 , wherein
 the computing the exposure latitude includes estimating a standard deviation of values of the mask characteristic obtained when mask patterns included in said each chip pattern are used as a population, based on actually measured values of the mask characteristic of samples extracted from the population, and   the exposure latitude is computed based on the standard deviation.   
   
   
       27 . The method for manufacturing a semiconductor device according to  claim 21 , wherein the mask characteristic includes at least one of a CD (critical dimension) of said each chip pattern, a phase difference of said each chip pattern, and a transmittance of said each chip pattern.