US2010109050A1PendingUtilityA1
Field effect transistor with independently biased gates
Est. expiryApr 18, 2026(expired)· nominal 20-yr term from priority
H10D 64/411H10D 30/4732
49
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Claims
Abstract
A field effect transistor (FET) having at least two independently biased gates can provide uniform electric field in the channel region of the FET. The same AC voltage may be applied to each gate for modulating the FET. One of the gates is positioned closer to the channel region than the other gate. Such a FET allows tailoring the electric field in the channel region of the FET so that it is substantially uniform. The FET exhibits desirable performance characteristics, including having a constant transconductance.
Claims
exact text as granted — not AI-modified1 . A field effect transistor, comprising:
a channel region; a first gate biased at a first DC voltage; and a second gate biased at a second DC voltage and positioned farther from the channel region than the first gate.
2 . The field effect transistor of claim 1 , wherein the first DC voltage is greater than the second DC voltage.
3 . The field effect transistor of claim 1 , further comprising:
a source; and a drain; wherein the first gate is positioned closer to the source than to the drain.
4 . The field effect transistor of claim 1 , further comprising:
a semiconductor region; wherein the first gate forms a Schottky contact with the semiconductor region.
5 . The field effect transistor of claim 1 , further comprising:
a semiconductor region; wherein the second gate is positioned within approximately 1000 angstroms of the semiconductor region.
6 . The field effect transistor of claim 5 , wherein the second gate is positioned within approximately 100 angstroms of the semiconductor region.
7 . The field effect transistor of claim 1 , wherein the field effect transistor is a high-electron-mobility transistor.
8 . The field effect transistor of claim 1 , wherein the field effect transistor is a metal-oxide-semiconductor field effect transistor.
9 . A field effect transistor, comprising:
a source; a drain; a semiconductor region; a first gate biased at a first DC voltage and contacting the semiconductor region; and a second gate biased at a second DC voltage lower than the first DC voltage, the second gate being separated from the semiconductor region by an insulating region.
10 . The field effect transistor of claim 9 , wherein the field effect transistor is a high-electron-mobility transistor.
11 . The field effect transistor of claim 9 , wherein the second gate is separated from the semiconductor region by less than approximately 1000 angstroms of the insulating region.
12 . The field effect transistor of claim 11 , wherein the second gate is separated from the semiconductor region by approximately 100 angstroms or less of the insulating region.
13 . The field effect transistor of claim 9 , wherein at least a portion of the second gate is positioned above the first gate.
14 . The field effect transistor of claim 9 , wherein the first gate is positioned closer to the source than the second gate.
15 . The field effect transistor of claim 9 , wherein the second gate is positioned closer to the drain than the first gate.
16 . The field effect transistor of claim 9 , wherein the first gate is separated from both the first gate and the semiconductor region by a same distance of approximately 100 angstroms or less of the insulating region.
17 . The field effect transistor of claim 9 , further comprising a third gate biased at a third DC voltage and separated from the semiconductor region by an insulating region.
18 . The field effect transistor of claim 1 , wherein the field effect transistor operates with substantially constant transconductance.
19 . The field effect transistor of claim 18 , wherein the substantially constant transconductance varies by no more than 25 mS/mm over a range of gate bias voltages spanning at least one volt.
20 . The field effect transistor of claim 9 , wherein the field effect transistor operates with substantially constant transconductance.Join the waitlist — get patent alerts
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