Method for reducing poly-depletion in dual gate cmos fabrication process

Abstract

Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps.

1 . A method for reducing poly-depletion in a dual gate CMOS fabrication process, comprising the steps of:
 forming an STI oxide film at proper sites of a silicon substrate having an NMOS forming region and a PMOS forming region;   sequentially forming a gate dielectric film and a polysilicon film on the silicon substrate including the STI oxide film;   selectively implanting an N-type impurity and a P-type impurity into the portions of the polysilicon film, which correspond respectively to the NMOS forming region and PMOS forming region of the silicon substrate, by ion implantation; and   patterning the polysilicon film having the selectively ion-implanted N-type and P-type impurities and the gate dielectric film to form an N+ polysilicon gate in the NMOS region of the silicon substrate and a P+ polysilicon gate in the PMOS region of the silicon substrate, wherein the height of the STI oxide film measured at the top of the silicon substrate is less or equal to 0.   
   
   
       2 . The method according to  claim 1 , wherein the height of said STI oxide film is adjusted by increasing a target polishing amount of CMP when forming the STI oxide film or by wet etching the surface of the STI oxide film after formation of the film. 
   
   
       3 . A method for reducing poly-depletion in a dual gate CMOS fabrication process, comprising the steps of:
 forming an STI oxide film at proper sites of a silicon substrate having an NMOS forming region and a PMOS forming region;   sequentially forming a gate dielectric film and a polysilicon film on the silicon substrate including the STI oxide film;   selectively implanting an N-type impurity and a P-type impurity into the portions of the polysilicon film, which correspond respectively to the NMOS forming region and PMOS forming region of the silicon substrate, by ion implantation; and   patterning the polysilicon film having the selectively ion-implanted N-type and P-type impurities and the gate dielectric film to form an N+ polysilicon gate in the NMOS region of the silicon substrate and a P+ polysilicon gate in the PMOS region of the silicon substrate, wherein the formation of the polysilicon film and the ion-implantation of the impurities are repeated at least twice.   
   
   
       4 . The method according to  claim 3 , wherein said polysilicon film has a final thickness ranging from 1900 to 2100 Å. 
   
   
       5 . The method according to  claim 4 , wherein said final thickness of the polysilicon film is identical to the sum of the thicknesses obtained in every repeated polysilicon film formation.