Method and system for precise-clock synchronization, and device for precise-clock frequency/time synchronization

Abstract

A precise-clock synchronization method and system and a precise-clock frequency/time synchronization device are provided. In the embodiments of the present invention, two time stamp engines are provided at a slave clock side. A relative time stamp engine provides a relative arrival time stamp. An absolute time stamp engine provides an absolute arrival time stamp. The frequency/time synchronization is calculated by using different time stamps obtained from different time stamp engines, so the frequency synchronization and time synchronization of master clock and the slave clock may be separately accomplished, and one synchronization function may be enabled or disabled. Therefore, the frequency synchronization and time synchronization of the master clock and the slave clock do not interfere with each other, thus greatly reducing the occupied link bandwidth resources.

1 . A precise-clock synchronization method, comprising:
 obtaining a time stamp, wherein the time stamp comprises at least an original time stamp about the time when a master clock side transmits a Sync packet and a relative arrival time stamp about the time when a slave clock side receives the Sync packet;   determining whether a clock frequency at the slave clock side is synchronous with a clock frequency at the master clock side or not according to the original time stamp and its corresponding relative arrival time stamp;   synchronizing the clock frequency at the slave clock side with the clock frequency at the master clock side, if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous.   
     
     
         2 . The precise-clock synchronization method according to  claim 1 , wherein the synchronizing the clock frequency at the slave clock side with the clock frequency at the master clock side comprises:
 calculating a relative delay between the relative arrival time stamp and the original time stamp;   setting a first statistics period having a minimum relative delay selected from a plurality of calculated relative delays;   setting a second statistics period, and monitoring a changing trend of the minimum relative delay within the second statistics period;   determining whether the clock frequency at the slave clock side and the clock frequency at the master clock side are synchronous or not according to the changing trend of the minimum relative delay.   
     
     
         3 . The precise-clock synchronization method according to  claim 2 , wherein if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous, the method comprises:
 determining that the clock frequency at the slave clock side and the clock frequency at the master clock side are not synchronous, if the values of two adjacent minimum relative delays are not substantially the same.   
     
     
         4 . The precise-clock synchronization method according to  claim 2 , wherein the calculating a relative delay between the relative arrival time stamp and the original time stamp comprises:
 getting the relative delay through calculating the absolute value of the difference between the relative arrival time stamp and the original time stamp.   
     
     
         5 . The precise-clock synchronization method according to  claim 2 , wherein before setting the second statistics period, the method further comprises:
 filtering the selected minimum relative delay.   
     
     
         6 . The precise-clock synchronization method according to  claim 1 , wherein the determining whether a clock frequency at the slave clock side is synchronous with a clock frequency at the master clock side or not according to the original time stamp and its corresponding relative arrival time stamp comprises:
 comparing a time interval of adjacent original time stamps with a time interval of similar corresponding adjacent relative arrival time stamps;   determining whether a clock frequency at a slave clock side and a clock frequency at the master clock side are synchronous or not according to a comparison result.   
     
     
         7 . The precise-clock synchronization method according to  claim 6 , wherein if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous, the method comprises:
 determining that the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous, if the time interval of original time stamps is different from the time interval of relative arrival time stamps.   
     
     
         8 . The precise-clock synchronization method according to  claim 1 , wherein obtaining a time stamp comprises:
 receiving the Sync packet transmitted by a master clock side;   transmitting a Delay_Req packet, and receiving a Delay_Resp packet returned by the master clock side after it receives the Delay_Req packet;   obtaining the time stamp including the original time stamp, the relative arrival time stamp and an absolute arrival time stamp of the Sync packet, a Delay_Resp time stamp, and a Delay_Req time stamp; and   calculating a time offset according to the original time stamp, the absolute arrival time stamp, the Delay_Resp time stamp, and the Delay_Req time stamp.   
     
     
         9 . The precise-clock synchronization method according to  claim 8 , wherein the method further comprises:
 receiving a time synchronization enable signal after the synchronization between the clock frequency at the slave clock side and the clock frequency at the master clock;   synchronizing the clock time at the slave clock side with the clock time at the master clock side by using the time offset.   
     
     
         10 . The precise-clock synchronization method according to  claim 1 , wherein the method further comprises:
 receiving a time synchronization enable signal after the synchronization between the clock frequency at the slave clock side and the clock frequency at the master clock side;   transmitting a Delay_Req at the time when the time synchronization enable signal is received, and receiving a Delay_Resp returned by the master clock side after it receives the Delay_Req;   obtaining the time stamp including the original time stamp, and an absolute arrival time stamp of the Sync packet, a Delay_Resp time stamp, and a Delay_Req time stamp;   calculating a time offset according to the original time stamp, the absolute arrival time stamp, the Delay_Resp time stamp, and the Delay_Req time stamp; and   synchronizing the clock time at the slave clock side with the clock time at the master clock side by using the time offset.   
     
     
         11 . A precise-clock frequency synchronization device, comprising:
 a relative time stamp engine, adapted to provide a relative arrival time stamp about the time when the slave clock side receives a Sync packet;   a first obtaining module, adapted to obtain a time stamp, wherein the time stamp comprises at least an original time stamp about the time when the master clock side transmits each Sync packet and the relative arrival time stamp about the time when the slave clock side receives the Sync packet;   a judging module, adapted to judge whether the clock frequency at the slave clock side and the clock frequency at the master clock side are synchronous or not according to the each original time stamp and its corresponding relative arrival time stamp;   a frequency adjusting module, adapted to synchronize the clock frequency at the slave clock side with the clock frequency at the master clock side, if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous.   
     
     
         12 . The precise-clock frequency synchronization device according to  claim 11 , wherein the judging module comprises:
 a first calculating module, adapted to calculate a relative delay between the relative arrival time stamp and the original time stamp;   a comparing/selecting module, adapted to select a minimum relative delay from a plurality of calculated relative delays within a first statistics period;   a monitoring module, adapted to monitor changes of the plurality of minimum relative delays within a second statistics period;   a change judging module, adapted to judge whether the clock frequency at the slave clock side and the clock frequency at the master clock side are synchronous or not according to a changing trend of the plurality of minimum relative delay.   
     
     
         13 . The precise-clock frequency synchronization device according to  claim 12 , wherein the precise-clock frequency synchronization device further comprises a timing module adapted to set the first statistics period and the second statistics period. 
     
     
         14 . A precise-clock time synchronization device, comprising:
 an absolute time stamp engine, adapted to provide an absolute arrival time stamp about the time when a slave clock side receives a Sync packet and a Delay_Req time stamp about the time when the slave clock side transmits a Delay_Req;   a second obtaining module, adapted to obtain an original time stamp and an absolute arrival time stamp of the Sync packet transmitted by the master clock side, a Delay_Resp time stamp transmitted by the master clock side, and a Delay_Req time stamp transmitted by the slave clock side;   a second calculating module, adapted to calculate a time offset according to the obtained original time stamp, the absolute arrival time stamp, the Delay_Req time stamp, and the Delay_Resp time stamp;   a time adjusting module, adapted to synchronize the clock time at the slave clock side with the clock time at the master clock side by using the time offset.   
     
     
         15 . The precise-clock time synchronization device according to  claim 14 , wherein the precise-clock time synchronization device further comprises a receiving module adapted to receive a time synchronization enable signal. 
     
     
         16 . A precise-clock synchronization system, comprising:
 a precise-clock frequency synchronization device, adapted to synchronize a clock frequency at a slave clock side with a clock frequency at a master clock side, according to an original time stamp about a time when the master clock side transmits a Sync packet and a relative arrival time stamp about a time when the slave clock side receives the Sync packet;   a precise-clock time synchronization device, adapted to calculate a time offset according to the original time stamp of the Sync packet and an absolute arrival time stamp about the time when the slave clock side receives the Sync packet, as well as a Delay_Req time stamp and a Delay_Resp time stamp, and adjust the clock time at the slave clock side to be synchronous with the clock time at the master clock side by using the time offset.   
     
     
         17 . The precise-clock synchronization system according to  claim 16 , wherein the precise-clock frequency synchronization device comprises:
 a relative time stamp engine, adapted to provide a relative arrival time stamp about the time when the slave clock side receives the Sync packet;   a first obtaining module, adapted to obtain a time stamp, wherein the time stamp comprises at least the original time stamp about the time when the master clock side transmits the Sync packet and the relative arrival time stamp about the time when the slave clock side receives the Sync packet;   a judging module, adapted to determine whether the clock frequency at the slave clock side and the clock frequency at the master clock side are synchronous or not according to the original time stamp and its corresponding relative arrival time stamp;   a frequency adjusting module, adapted to synchronize the clock frequency at the slave clock side with the clock frequency at the master clock side, if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous.   
     
     
         18 . The precise-clock synchronization system according to  claim 16 , the precise-clock time synchronization device comprises:
 an absolute time stamp engine, adapted to provide an absolute arrival time stamp about the time when the slave clock side receives the Sync packet and the Delay_Req time stamp about the time when the slave clock side transmits a Delay_Req;   a second obtaining module, adapted to obtain an original time stamp and an absolute arrival time stamp of the Sync packet transmitted by the master clock side, a Delay_Resp time stamp transmitted by the master clock side, and a Delay_Req time stamp transmitted by the slave clock side;   a second calculating module, adapted to calculate a time offset according to the obtained original time stamp, the absolute arrival time stamp, the Delay_Req time stamp, and the Delay_Resp time stamp;   a time adjusting module, adapted to synchronize the clock time at the slave clock side with the clock time at the master clock side by using the time offset.   
     
     
         19 . A computer readable media, comprising logic encoded in the computer readable media, the logic when executed by a processor, instructing the processor to:
 obtain a time stamp, wherein the time stamp comprises at least an original time stamp about a time when a master clock side transmits each Sync packet and a relative arrival time stamp about a time when a slave clock side receives each Sync packet;   judge whether a clock frequency at the slave clock side is synchronous with a clock frequency at the master clock side or not according to the original time stamp and its corresponding relative arrival time stamp; and   synchronizing the clock frequency at the slave clock side with the clock frequency at the master clock side, if the clock frequency at the slave clock side and the clock frequency at the master clock side are asynchronous.