Prevention of plasma induced damage arising from etching of crack stop trenches in multi-layered low-k semiconductor devices

Abstract

A method of fabricating a semiconductor device begins by forming a lower interconnection dielectric on a substrate and forming at least one active or passive device in the lower interconnection dielectric. An etch stop layer is formed on the lower interconnection dielectric and an interconnect stack layer is formed on the etch stop layer. At least one interconnect trench structure and at least one crack stop trench are etched in the interconnect stack layer while maintaining electrical isolation between the interconnect structure and the crack stop trench.

1 . A semiconductor wafer comprising:
 a lower interconnection dielectric located on a substrate;   at least one active or passive device formed in the lower interconnection dielectric;   at least one electrical isolating region formed in the lower interconnection dielectric;   an etch stop layer located over the lower interconnection dielectric;   an interconnect stack layer located over the etch stop layer;   at least one interconnect trench structure located in the interconnect stack layer; and   at least one crack stop trench located in the interconnect stack layer over the electrical isolating region,
 wherein the at least one crack stop trench is continuous and extends around a periphery of an individual die area. 
   
   
   
       2 . The wafer of  claim 1 , wherein the electrically isolating region comprises a gate dielectric layer. 
   
   
       3 . The wafer of  claim 1 , wherein the substrate is a SOI substrate. 
   
   
       4 . The wafer of  claim 3 , wherein the SOI substrate includes a buried oxide layer that serves as an electrically isolating region that facilitates maintenance of the electrical isolation between the interconnect structure and the crack stop trench during etching. 
   
   
       5 . The wafer of  claim 1 , wherein the interconnect stack layer comprises a low k dielectric material. 
   
   
       6 . The wafer of  claim 5 , wherein the low k dielectric material includes an organosilicon material. 
   
   
       7 . The wafer of  claim 1 , wherein the etch stop layer is formed of at least one of SiC, SiN, and SiCN. 
   
   
       8 . The wafer of  claim 5 , wherein the dielectric material is formed using chemical vapor deposition. 
   
   
       9 . The wafer of  claim 1 , further comprising a capping layer on the interconnect stack layer. 
   
   
       10 . The wafer of  claim 9 , wherein the capping layer is formed of at least one of SiO 2 , SiOF, SiON, SiC, SiN and SiCN. 
   
   
       11 . The wafer of  claim 1 , wherein said at least one electrical isolating region comprises a polysilicon gate and a gate dielectric. 
   
   
       12 . The wafer of  claim 1 , wherein the substrate comprises a composite substrate. 
   
   
       13 . The wafer of  claim 12 , wherein the composite substrate comprises two silicon layers, one thinner than the other, separated by a silicon oxide layer. 
   
   
       14 . The wafer of  claim 1 , wherein said at least one crack stop trench includes a barrier layer. 
   
   
       15 . The wafer of  claim 1 , wherein said barrier layer comprises tantalum, tantalum nitride, titanium, titanium silicide or zirconium. 
   
   
       16 . The wafer of  claim 1 , wherein a copper conductive layer is formed on said barrier layer. 
   
   
       17 . The wafer of  claim 1 , wherein the substrate comprises a gallium arsenic substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate.