Semiconductor device and its manufacture method

Abstract

A semiconductor device includes non-volatile memory cells and a peripheral circuit including field effect transistors having an insulated gate. The semiconductor device has memory cells with a high retention ability and field effect transistors having an insulated gate with large drive current. The semiconductor device has a semiconductor substrate ( 1 ) having first and second areas (AR 1 , AR 2 ), a floating gate structure ( 4, 5, 6, 7, 8 ) for a non-volatile memory cell, a control gate structure ( 14 ) formed coupled to the floating gate structure, formed in the first area, and an insulated gate electrode ( 12, 14 ) for a logical circuit formed in the second area, wherein the floating gate structure has bird's beaks larger than those of the insulated gate electrode.

1 . A semiconductor device comprising:
 a semiconductor substrate having on a surface thereof a first element area, a second element area, and a third element area separated by shallow trench isolation;   a first transistor having a first gate structure in said first element area, side walls of said first gate structure being covered with a first thermally oxidized film;   a second transistor having a second gate structure in said second element area, and having no bird's beak; and   a third transistor having a third gate structure in said third element area, side walls of said third gate structure being covered with a second thermally oxidized film, and having thermally oxidized gate bird's beaks under edge region of the third gate structure;   wherein said first transistor operates as a non-volatile memory cell, said second transistor operates as a low voltage logical circuit element, and said third transistor operates as a high voltage logical circuit element.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein said first gate structure includes a first gate insulating film formed above said first area and including thermally oxidized gate bird's beaks under edge regions of the first gate structure, a floating gate formed of a first silicon layer formed on said first gate insulating film, a second gate insulating film formed on said first silicon layer and a control gate formed of a second silicon layer formed on said second gate insulating film. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein said second gate insulating film includes an insulating lamination of an oxide film, a nitride film and an oxide film. 
     
     
         4 . A semiconductor device comprising:
 a semiconductor substrate having on a surface thereof a first element area, a second element area, and a third element area, separated by shallow trench isolation;   a first transistor having a first gate structure in said first element area, side walls of said first gate structure being covered with a thermally oxidized film, and said thermally oxidized film and said first gate structure being covered with a deposited oxide film;   a second transistor having a second gate structure in said second element area, side walls of said second gate structure being covered with said deposited oxide film, but top surface of said second gate structure being not covered with said deposited oxide film, and said second gate structure having no gate bird's beak,   a third transistor having a third gate structure in said third element area, side walls of said third gate structure being covered with said deposited oxide film, but top surface of said third gate structure being not covered with said deposited oxide film,   wherein said first transistor operates as a non-volatile memory cell, said second transistor operates as a low voltage logical circuit element, and said third transistor operates as a high voltage logical circuit element.   
     
     
         5 . The semiconductor device according to  claim 4 , wherein said first gate structure includes a gate insulating film formed above said first element area and including thermally oxidized gate bird's beaks under edge portions of the first gate structure.