Contact structure of a wires and method manufacturing the same, and thin film transistor substrate including the contact structure and method manufacturing the same
Abstract
In a method of fabricating a thin film transistor array substrate for a liquid crystal display, a gate line assembly is formed on a substrate with a chrome-based under-layer and an aluminum alloy-based over-layer while proceeding in the horizontal direction. The gate line assembly has gate lines, and gate electrodes, and gate pads. A gate insulating layer is deposited onto the insulating substrate such that the gate insulating layer covers the gate line assembly. A semiconductor layer and an ohmic contact layer are sequentially formed on the gate insulating layer. A data line assembly is formed on the ohmic contact layer with a chrome-based under-layer and an aluminum alloy-based over-layer. The data line assembly has data lines crossing over the gate lines, source electrodes, drain electrodes, and data pads. A protective layer is deposited onto the substrate, and patterned to thereby form contact holes exposing the drain electrodes, the gate pads, and the data pads. The sidewall of the under-layers for the gate line assembly and the data line assembly is exposed through the contact holes. An IZO-based layer is deposited onto the substrate, and patterned to thereby form pixel electrodes, subsidiary gate pads, and subsidiary data pads. The pixel electrodes are connected to the sidewall of the drain electrodes, and the subsidiary gate and data pads are connected to the sidewall of the gate and the data pads.
Claims
exact text as granted — not AI-modified1 . A wiring line contact structure comprising:
a wiring line assembly disposed on a first insulating layer and including an under-layer and an over-layer, the over-layer having edges located on the under-layer, a second insulating layer on the wiring line assembly and having a contact hole exposing at least a portion of the under-layer, and a conductive layer formed on the second insulating layer and contacting both the under-layer and a top surface of the over-layer through the contact hole.
2 . The wiring line contact structure of claim 1 , wherein the contact hole exposes at least a portion of an edge of the under-layer.
3 . The wiring line contact structure of claim 2 , wherein an edge of the under-layer comprises two sides meeting at a vertex and an edge of the contact hole crosses the two sides of the under-layer, or an edge of the contact hole comprises two sides meeting at a vertex and an edge of the under-layer crosses the two sides of the contact hole.
4 . The wiring line contact structure of claim 2 , wherein an edge of the under-layer includes a stepwise-shaped portion, and the contact hole exposes at least a portion of the stepwise-shaped portion of the under-layer.
5 . The wiring line contact structure of claim 2 , wherein an edge of the under-layer includes a dent portion, and the contact hole exposes at least a portion of the dent portion of the under-layer.
6 . The wiring line contact structure of claim 2 , wherein the under-layer includes two opposing sides, and the contact hole exposes at least a portion of the two opposing sides of the under-layer.
7 . The wiring line contact structure of claim 1 , wherein the over-layer includes an opening that exposes a portion of the under-layer.
8 . The wiring line contact structure of claim 7 , wherein the over-layer includes at least one opening that respectively exposes a portion of the under-layer.
9 . The wiring line contact structure of claim 9 , wherein the opening of the over-layer has a size of 4 μm×4 μm or less.
10 . The wiring line contact structure of claim 1 , wherein the contact hole has a size from 4 μm×4 μm to 10 μm×10 μm.
11 . The wiring line contact structure of claim 1 , wherein the under-layer comprises Mo, Mo alloy, Cr or Cr alloy.
12 . The wiring line contact structure of claim 1 , wherein the over-layer comprises Al or Al alloy.
13 . The wiring line contact structure of claim 1 , wherein the conductive layer comprises ITO or IZO.Join the waitlist — get patent alerts
Track US2010096176A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.