US2010095089A1PendingUtilityA1

Multiprocessor system with multiport memory

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Oct 14, 2008Filed: Oct 12, 2009Published: Apr 15, 2010
Est. expiryOct 14, 2028(~2.2 yrs left)· nominal 20-yr term from priority
Inventors:Jin-Hyoung Kwon
G06F 13/00G06F 12/08G06F 9/46G06F 9/544G06F 15/167
48
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Claims

Abstract

A multiprocessor system includes first and second processors independently executing application functions associated with one or more applications using an open operating system (OS), a multiport memory, a first nonvolatile memory coupled to the first processor via a first bus, and a second nonvolatile memory coupled to the second processor via a second bus. The multiport memory includes a memory cell array divided into a plurality of memory banks including a shared memory bank commonly accessed by the first and second processors via respective first and second ports, and an internal register disposed outside the memory cell array and configured to control access authority to the shared memory bank by the first and second processors, wherein different application functions are independently executed in parallel by the first and second processors using the multiport memory as a data transfer mechanism.

Claims

exact text as granted — not AI-modified
1 . A multiprocessor system comprising:
 first and second processors independently executing application functions associated with one or more applications using an open operating system (OS);   a multiport memory comprising:
 a memory cell array divided into a plurality of memory banks including a shared memory bank commonly accessed by the first and second processors via respective first and second ports, and 
 an internal register disposed outside the memory cell array and configured to control access authority to the shared memory bank by the first and second processors; and 
   a first nonvolatile memory coupled to the first processor via a first bus and a second nonvolatile memory coupled to the second processor via a second bus,   wherein different application functions are independently executed in parallel by the first and second processors using the multiport memory as a data transfer mechanism.   
   
   
       2 . The system of  claim 1 , wherein the first processor is a MODEM processor exclusively executing a communication application. 
   
   
       3 . The system of  claim 2 , wherein the second processor is an application processor executing at least one application associated with an image display, a digital still camera, or an MP3 file playback. 
   
   
       4 . The system of  claim 2 , wherein the first processor executes an application function in response to message communicated from the second processor via the shared memory bank of the multiport memory. 
   
   
       5 . The system of  claim 2 , wherein the communication application enable execution of a data modulation/demodulation function. 
   
   
       6 . The system of  claim 3 , wherein the at least one application comprises an application function enabling at least one application function including a movie file playback, message edition, digital still cameral image display and an MP3 file playback. 
   
   
       7 . The system of  claim 1 , wherein the internal register comprises a semaphore area configured to store access authority information, and mailbox areas configured to store request information and a message related to an access authority request. 
   
   
       8 . The system of  claim 1 , wherein the multiport memory further comprises:
 a dedicated memory bank accessed by only the first processor or the second processor.   
   
   
       9 . The system of  claim 1 , wherein the first and second nonvolatile memories are flash memory.

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