Circuit and method for sampling valid command using extended valid address window in double pumped address scheme memory device

Abstract

Provided are a circuit and method for sampling a valid command using a valid address window extended for a high-speed operation in a double pumped address scheme memory device. A method for extending the valid address window includes: inputting a valid command signal and a first address signal at the first cycle of a clock signal; inputting a second address signal at the second cycle of the clock signal; generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and latching and decoding the extended first and second internal address signals in response to the decoded command signal.

1 . A method for extending a valid address window comprising:
 inputting a valid command signal and a first address signal at the first cycle of a clock signal;
 inputting a second address signal at the second cycle of the clock signal; 
   generating a decoded command signal and extended first and second internal address signals respectively in response to the command signal and the address signals; and
 latching and decoding the extended first and second internal address signals in response to the decoded command signal, 
 wherein the valid window of the extended first and second internal address signals corresponds to at least two clock cycles of the clock signal. 
   
   
   
       2 . The method of  claim 1 , wherein the valid window of the decoded command signal corresponds to at least one clock cycle of the clock signal. 
   
   
       3 . The method of  claim 1 , wherein the valid address window extending method is applied to a double pumped address scheme memory device.