Data receiver of semiconductor integrated circuit

Abstract

A data receiver of a semiconductor integrated circuit is configured to detect received data using an equalization function, wherein the data receiver is configured to stop the equalization function during a period in which the data is not received.

1 . A data receiver of a semiconductor integrated circuit, being configured to detect received data using an equalization function,
 wherein the data receiver is configured to stop the equalization function during a period in which the data is not received.   
   
   
       2 . The data receiver of  claim 1  comprising:
 an amplifier configured to output an amplified signal by detecting and amplifying the data using the equalization function according to feedback data;   a detecting unit configured to detect the period in which data is not received in the amplifier and output a detecting signal; and   an equalization function control unit configured to stop the equalization function of the amplifier in response to the detecting signal.   
   
   
       3 . The data receiver of  claim 2 , wherein the detecting unit is configured to detect the period in which data is not received by the amplifier according to the level of the amplified signal. 
   
   
       4 . The data receiver of  claim 3 , wherein the detecting unit comprises:
 a first switching element configured to output a signal at a first logic level when the level of the amplified signal is above a first voltage level;   a second switching element configured to output a signal at a second logic level when the level of the amplified signal is less than the first voltage level; and   a logic circuit configured to output the detecting signal by combining the output of the first switching element and the output of the second switching element.   
   
   
       5 . The data receiver of  claim 4 , wherein the first voltage level includes a middle level between a power voltage level and a ground voltage level. 
   
   
       6 . The data receiver of  claim 5 , wherein the first switching element is a transistor with a gate configured to receive the amplified signal, a source configured to be applied with the ground voltage, and a drain configured to be applied with the power voltage through a first resistor. 
   
   
       7 . The data receiver of  claim 5 , wherein the second switching element is a transistor with a gate configured to receive the amplified signal, a source configured to be applied with the power voltage, and a drain configured to be applied with the ground voltage through a second resistor. 
   
   
       8 . The data receiver of  claim 4 , wherein the logic circuit is configured to output the detecting signal by performing an AND operation on an inverted signal obtained by inverting the signal of first logic level, and the signal of second logic level. 
   
   
       9 . The data receiver of  claim 2 , wherein the equalization function control unit is configured to stop an equalization function of the amplifier by controlling the level of the feedback data in response to the detecting signal. 
   
   
       10 . The data receiver of  claim 9 , wherein the equalization function control unit is configured to change a voltage level of the feedback data to the ground voltage level in response to the detecting signal. 
   
   
       11 . The data receiver of  claim 10 , wherein the equalization function control unit includes switching elements that connect signal lines to terminals of the ground voltage, wherein the signal lines are configured to transmit the feedback data in response to the detecting signal.