Memory devices including semiconductor pillars

Abstract

One embodiment relates to an integrated circuit that includes a memory array of pillars arranged in rows and columns. The pillars are separated from one another by row trenches and column trenches. The column trenches include a pair of parallel column trenches. A first trench of the pair includes two parallel bit lines coupled to pillars adjacent to the first trench. A second trench of the pair is free of bit lines. Other methods, devices, and systems are also disclosed.

1 . An integrated circuit including a memory cell on a semiconductor body, the memory cell comprising:
 a semiconductor pillar having a number of sides, the pillar comprising: a body region vertically disposed between an upper source/drain region and a lower source/drain region;   a metal body alongside a first side of the semiconductor pillar, the metal body coupled to the upper or lower source/drain region;   a body region contact associated with a second side of the semiconductor pillar opposite the first side, the body region contact coupled to the body region.   
   
   
       2 . The integrated circuit of  claim 1 , where the body region contact is disposed in the pillar, the body region contact extending downward from the body region to the semiconductor body under the lower source/drain region. 
   
   
       3 . The integrated circuit of  claim 1 , where the body region contact is disposed in a trench abutting the second side of the pillar, the body region contact comprising a conductive material and extending from the body region to the semiconductor body under the lower source/drain region. 
   
   
       4 . The integrated circuit of  claim 3 , further comprising:
 an isolation region abutting the second side of the semiconductor pillar, the isolation region adapted to electrically isolate the body region contact from the lower source/drain region.   
   
   
       5 . The integrated circuit of  claim 1 , further comprising:
 a wordline adjacent to the body region, where a gate dielectric is disposed between the wordline and the body region.   
   
   
       6 . The integrated circuit of  claim 1 , further comprising:
 a memory storage element disposed atop the pillar.   
   
   
       7 . The integrated circuit of  claim 1 , where the metal body is disposed in a recessed surface, the recessed surface extending laterally into the first side of the semiconductor pillar at the lower source/drain region. 
   
   
       8 . An integrated circuit including a memory array, the memory array comprising:
 a semiconductor body including an array of semiconductor pillars arranged in a series of rows and columns, where column trenches and row trenches extend beneath the semiconductor body to separate the pillars;   a first column trench disposed between pillars of a first column and pillars of a second column; the pillars of the first column adjacent to a first side of the first column trench, and the pillars of the second column adjacent to a second side of the first column trench; and   a pair of parallel conductive bodies disposed within the first column trench and electrically isolated from one another, a first conductive body of the pair coupled to pillars of the first column, and a second conductive body of the pair coupled to pillars of the second column.   
   
   
       9 . The integrated circuit of  claim 8 , where the first and second conductive bodies are separate metal bitlines of the memory array. 
   
   
       10 . The integrated circuit of  claim 8 , further comprising:
 a second column trench disposed between pillars of the second column and pillars of a third column, the pillars of the second column adjacent to a first side of the second column trench and the pillars of the third column adjacent to a second side of the second column trench;   where the second column trench is free of bitlines.   
   
   
       11 . The integrated circuit of  claim 10 , where the second column trench includes at least one body contact coupled to a body region in at least one pillar adjacent to the second column trench. 
   
   
       12 . The integrated circuit of  claim 8 , where a pillar in the second column comprises:
 a lower source/drain region having a first conductivity type to which the second conductive body is coupled;   an upper source/drain region having the first conductivity type; and   a body region disposed vertically between the lower and upper source/drain regions, the body region having a second conductivity type that is opposite the first conductivity type.   
   
   
       13 . The integrated circuit of  claim 12 , further comprising:
 a body region contact associated with a second column trench, the second column trench disposed about an opposing side of the second column relative to the first column trench.   
   
   
       14 . The integrated circuit of  claim 13 , where the body region contact is disposed in the pillar and electrically isolated from a wordline disposed over the body region contact, the body region contact having the second conductivity type and extending downward from the body region to a substrate under the lower source/drain region. 
   
   
       15 . The integrated circuit of  claim 13 , where the body region contact abuts pillars in the second column and abuts pillars in a third column, the third column adjacent to the second column. 
   
   
       16 . The integrated circuit of  claim 13 , further comprising:
 an isolation region abutting the opposing side of the second column of pillars and isolating the body region contact from the lower source/drain region.   
   
   
       17 . The integrated circuit of  claim 12 , where lower source/drain regions extend continuously between pillars along the second column. 
   
   
       18 . The integrated circuit of  claim 12 , further comprising:
 a conductive wordline disposed in a row trench traversing the pair of conductive bodies, the conductive wordline adjacent to the body region of the pillar and separated from the body region by a gate dielectric layer.   
   
   
       19 . The integrated circuit of  claim 18 , where the conductive wordline is arranged over the pair of conductive bodies. 
   
   
       20 . The integrated circuit of  claim 8 , where different pillars of the array have approximately the same height, length and width as one another. 
   
   
       21 . The integrated circuit of  claim 8 , further comprising:
 memory storage elements disposed atop respective semiconductor pillars.   
   
   
       22 . An integrated circuit, comprising:
 a memory array of pillars arranged in rows and columns, the pillars separated by row trenches and column trenches;   wherein the column trenches include a pair of parallel column trenches; a first trench of the pair comprising two parallel bit lines coupled to pillars adjacent to the first trench, and a second trench of the pair free of bit lines.   
   
   
       23 . The integrated circuit of  claim 22 , further comprising:
 a body contact region in the second trench.   
   
   
       24 . A method of forming an integrated circuit, comprising:
 forming in a semiconductor body a series of first column trenches lined with an insulating layer;   forming a pair of separate bitlines in each of the first column trenches;   forming a second column trench between two adjacent first column trenches;   forming a body contact in the second column trench.   
   
   
       25 . The method of  claim 24 , further comprising:
 forming row trenches that traverse over the column trenches; and   forming wordlines in the row trenches.   
   
   
       26 . The method of  claim 24 , where forming the pair of separate bitlines in a first column trench comprises:
 forming a metal body in the bottom of the first column trench;   forming spacers over the metal body to leave an exposed upper surface of the metal body between the spacers; and   removing the metal body beneath the exposed upper surface to fashion the pair of separate bitlines in the first column trench.   
   
   
       27 . The method of  claim 24 , further comprising forming separate contacts for the pair of separate bitlines in each of the first column trenches, the contacts isolated from one another by a dielectric in the first column trenches. 
   
   
       28 . The method of  claim 24 , where forming the second column trench further comprises:
 forming spacers to define an opening corresponding to a top region of the second column trench; and   performing an etch while the spacers are in place to form the second column trench.   
   
   
       29 . The method of  claim 28 , where forming the body contact comprises:
 implanting ions through the opening to define the body contact.   
   
   
       30 . The method of  claim 28 , where forming the body contact comprises:
 depositing or growing a conductive material in the bottom of the second column trench.