Image sensor and control method of the image sensor

Abstract

An image sensor has plural array blocks B 1 to B 20 arranged in a two dimensional (2D) arrangement. Each array block has a sub array and a corresponding analogue to digital (A/D) converter for performing an A/D conversion of light signals (or detection signals) output from the sub array. The sub array has plural picture element cells arranged in a 2D arrangement. Each A/D converter has a pulse delay circuit having delay units of plural stages connected in series. Each delay unit delays an input pulse by a delay time corresponding to a level of the light signals received from the sub array. A pulse delay type A/D converter is used as the A/D converter, which outputs the number of the delay units as an A/D conversion data item through which the input pulse passes for a measurement time period.

1 . An image sensor mounted on a single IC chip comprising:
 a light receiving element array in which a plurality of picture element cells are arranged in a two-dimension arrangement and divided into a plurality of sub arrays, and each picture element cell has at least a photoelectric conversion element; and   an analogue to digital (A/D) conversion section configured to perform A/D conversion of received light signals transferred from the light receiving element array, the A/D conversion section comprising a plurality of A/D converters, and each of the A/D converters being placed corresponding to each sub array.   
     
     
         2 . The image sensor according to  claim 1 , wherein
 each A/D converter is placed at an area adjacent to the corresponding sub array.   
     
     
         3 . The image sensor according to  claim 1 , wherein
 each A/D converter is placed at a peripheral section of the light receiving element array.   
     
     
         4 . The image sensor according to  claim 3 , wherein
 a pad configured to output data of each A/D converter is placed at the peripheral section of the light receiving element array, and   each A/D converter is placed at one of an area between the adjacent pads and an area at a bottom end of the pad.   
     
     
         5 . The image sensor according to  claim 1 , wherein each A/D converter comprises:
 a pulse delay circuit comprising a plurality of delay units connected in series as plural stages configured to delay a pulse signal by a delay time corresponding to the level of the light signal received from the corresponding sub array; and   a coding circuit configured to detect the number of the stages of the delay units through which the pulse signal passes during a measurement time period that is a period of a sampling clock signal (CKS) set in advance, and to generates and output A/D conversion data as numerical data corresponding to the number of the stages detected.   
     
     
         6 . The image sensor according to  claim 2 , wherein each A/D converter comprises:
 a pulse delay circuit comprising a plurality of delay units connected in series as plural stages configured to delay a pulse signal by a delay time corresponding to the level of the light signal received from the corresponding sub array; and   a coding circuit configured to detect the number of the stages of the delay units through which the pulse signal passes during a measurement time period that is a period of a sampling clock signal (CKS) set in advance, and to generates and output A/D conversion data as numerical data corresponding to the number of the stages detected.   
     
     
         7 . The image sensor according to  claim 3 , wherein each A/D converter comprises:
 a pulse delay circuit comprising a plurality of delay units connected in series as plural stages configured to delay a pulse signal by a delay time corresponding to the level of the light signal received from the corresponding sub array; and   a coding circuit configured to detect the number of the stages of the delay units through which the pulse signal passes during a measurement time period that is a period of a sampling clock signal that (CKS) in advance, and to generates and output A/D conversion data as numerical data corresponding to the number of the stages detected.   
     
     
         8 . The image sensor according to  claim 4 , wherein each A/D converter comprises:
 a pulse delay circuit comprising a plurality of delay units connected in series as plural stages configured to delay a pulse signal by a delay time corresponding to the level of the light signal received from the corresponding sub array; and   a coding circuit configured to detect the number of the stages of the delay units through which the pulse signal passes during a measurement time period that is a period of a sampling clock signal (CKS) set in advance, and to generates and output A/D conversion data as numerical data corresponding to the number of the stages detected.   
     
     
         9 . (canceled) 
     
     
         10 . The image sensor according to  claim 5 , wherein
 the pulse delay circuit comprises a ring-shaped time delay circuit in which the delay circuits are connected in series and in a ring connection, and   the coding circuit generates the A/D conversion data based on the number of circulations of the pulse signal through the ring-shaped time delay circuit during the measurement time period, and the position information of the pulse signal in the ring-shaped time delay circuit detected at the time of the completion of the measurement time period.   
     
     
         11 . (canceled) 
     
     
         12 . The image sensor according to  claim 5 , wherein
 the sampling clock signal (CKS) is in synchronization with a control dock signal (CKC) for generating control signals to be supplied to the light receiving element array in order to output the light signals received from the picture element cells in the light receiving element array.   
     
     
         13 . (canceled) 
     
     
         14 . The image sensor according to  claim 12 , wherein
 the control clock signal (CKC) is divided by 1/d (d in a positive integer) and the clock signals divided are used as the sampling clock signals (CKS).   
     
     
         15 . (canceled) 
     
     
         16 . The image sensor according to  claim 1 , wherein
 the light receiving element array is formed as one of a CMOS image sensor and a CCD image sensor.   
     
     
         17 . (canceled) 
     
     
         18 . An image sensor control method of controlling operation of an image sensor comprising:
 a light receiving element array; and   an A/D conversion section, the light receiving element array comprising “m” sub arrays, where m=n×k, m>n, and m, n, and k are positive integers, each sub array comprising picture element cells of a same number, each picture element cell comprising a photoelectric conversion element, and the A/D conversion section comprising a plurality of A/D converters, each A/D converter being provided for each sub array,   the image sensor control method comprising a step of performing an A/D conversion using only the sub arrays selected for a measurement time period that being given in advance, wherein   on the A/D conversion using only the sub arrays selected, the A/D conversion is executed k-times for each of the picture element cells forming the sub arrays selected, and   one of a summation value of and an average value of A/D conversion data items obtained from the k-times execution of the A/D conversions is used as the A/D conversion data to be output.   
     
     
         19 . An image sensor control method of controlling operation of an image sensor comprising:
 a light receiving element array; and   an A/D conversion section, the light receiving element array comprising “m” sub arrays, where m is a positive integer, each sub array comprising picture element cells of a same number, each picture element cell comprising a photoelectric conversion element, and the A/D conversion section comprising a plurality of A/D converters, each A/D converter being provided for each sub array,   the image sensor control method comprising a step of performing an A/D conversion using only the sub arrays selected for a measurement time period by which a resolution of A/D conversion data output from the A/D conversion section is changed, wherein   on the A/D conversion using only the sub arrays selected, the A/D conversion is executed for the measurement time period of “m/n” multiple times so as to output the A/D conversion data.