Non-volatile memory device and method of manufacturing the same

Abstract

In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

1 . A non-volatile memory device comprising:
 a tunnel insulating layer pattern on a channel region of a substrate;   a charge trapping layer pattern on the tunnel insulating layer pattern to trap electrons from the channel region;   a dielectric layer pattern on the charge trapping layer pattern;   a gate electrode on the dielectric layer pattern; and   spacers on sidewalls of the gate electrode, wherein the charge trapping layer pattern has a width smaller than a distance between outer surfaces of the spacers.   
   
   
       2 . The non-volatile memory device of  claim 1 , wherein the width of the charge trapping layer pattern is smaller than that of the tunnel insulating layer pattern. 
   
   
       3 . The non-volatile memory device of  claim 1 , wherein the width of the charge trapping layer pattern is smaller than that of the dielectric layer pattern. 
   
   
       4 . The non-volatile memory device of  claim 1 , wherein a width ratio of the charge trapping layer pattern to the gate electrode is about 0.7 to about 1.1. 
   
   
       5 . The non-volatile memory device of  claim 4 , wherein the width of the charge trapping layer pattern is substantially the same as that of the gate electrode. 
   
   
       6 . The non-volatile memory device of  claim 1 , wherein the charge trapping layer pattern is a silicon nitride layer pattern. 
   
   
       7 . The non-volatile memory device of  claim 1 , wherein the charge trapping layer pattern comprises any one selected from the group consisting of a metal oxide layer pattern, a metal oxynitride layer pattern, a metal silicon oxide layer pattern, and a metal silicon oxynitride layer pattern. 
   
   
       8 . The non-volatile memory device of  claim 7 , wherein the charge trapping layer pattern comprises at least one selected from the group consisting of hafnium(Hf), zirconium(Zr), tantalum(Ta), lanthanum(La), cerium (Ce), praseodymium(Pr), neodymium(Nd), samarium(Sm), europium(Eu), gadolinium(Gd), terbium(Tb), dysprosium(Dy), holmium(Ho), erbium(Er), thulium(Tm), ytterbium(Yb), and lutetium(Lu). 
   
   
       9 . The non-volatile memory device of  claim 1 , wherein the gate electrode has a multi-layered structure comprising a first metal nitride layer pattern, a second metal nitride layer pattern, and a metal layer pattern. 
   
   
       10 . The non-volatile memory device of  claim 1 , wherein the dielectric layer pattern is an aluminum oxide layer pattern.