Fabrication and structures of crystalline material

Abstract

A surface of the first semiconductor crystalline material has a reduced roughness. A semiconductor device includes a low defect, strained second semiconductor crystalline material over the surface of the first crystalline material. A surface of the strained second semiconductor crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters that reduce impurities at an interfacial boundary between the first and second semiconductor crystalline materials. In one embodiment, the first semiconductor crystalline material can be confined by an opening in an insulator having an aspect ratio sufficient to trap defects using Aspect Ratio Trapping techniques.

1 . A semiconductor device, comprising:
 a composite structure comprising a first semiconductor crystalline material interspersed with a high aspect ratio to a second material, the composite structure to have a planar surface; and   a strained second semiconductor crystalline material over the first semiconductor crystalline material at the planar surface, wherein the surface of the first semiconductor crystalline material has a surface roughness RMS of 5 nm or less, and wherein an interface between the first and second semiconductor crystalline materials has reduced impurity concentrations.   
   
   
       2 . The device of  claim 1 , wherein the surface of the second semiconductor crystalline material has a surface roughness RMS of about 4 nm or less, about 3 nm or less, about 1 nm or less, about 0.5 nm or less, or no greater than 0.3 nm. 
   
   
       3 . The device of  claim 1 , wherein the interface has reduced oxygen impurity concentrations. 
   
   
       4 . The device of  claim 1 , wherein the strain is along a longitudinal direction of the opening, perpendicular to the longitudinal direction or both along and perpendicular to the longitudinal. 
   
   
       5 . The device of  claim 1 , wherein the composite structure comprises: a semiconductor crystalline substrate;
 an insulator having an opening to the substrate;   the first semiconductor crystalline material within the opening in the insulator, the first semiconductor crystalline material being lattice-mismatched with the substrate.   
   
   
       6 . The device of  claim 5 , wherein the substrate is configured with depressions in the substrate, and wherein the insulator overlies sides of the depression to form said opening. 
   
   
       7 . The device of  claim 1  further comprising a CMOS device integrated with the substrate. 
   
   
       8 . The device of  claim 1 , wherein the crystalline material is a group III-V compound. 
   
   
       9 . The device of  claim 1 , wherein the interface between the first and second semiconductor crystalline materials is heat treated for a selected period of time at temperatures between 760° C. to 860° C. in H 2  gas. 
   
   
       10 . The device of  claim 1 , wherein the growing the second semiconductor crystalline material is strained Ge and the first semiconductor crystalline material a SiGe alloy. 
   
   
       11 . A method of manufacturing a semiconductor structure, comprising:
 providing a semiconductor crystalline substrate;   forming an insulator defining openings to a surface of the substrate; and   growing a first semiconductor crystalline material lattice-mismatched with the substrate within the openings of the insulator;   polishing a top surface of the first semiconductor crystalline material and the insulator;   growing a second semiconductor crystalline material over the polished first semiconductor crystalline material; and   heating the polished top surface at a selected temperature range to reduce impurities at the interface of the first and second semiconductor crystalline material.   
   
   
       12 . The method of  claim 11 , wherein the heating comprises heating at temperatures between 760° C. to 860° C. 
   
   
       13 . The method of  claim 11 , wherein the surface of the second semiconductor crystalline material has a surface roughness RMS of about 5 nm or less, about 3 nm or less, about 1 nm or less, about 0.5 nm or less, or no greater than 0.3 nm. 
   
   
       14 . The method of  claim 11 , wherein the interface has reduced oxygen impurity concentrations. 
   
   
       15 . The method of  claim 11 , wherein the second semiconductor crystalline material is elastically strained at least along a first direction relative to the opening, along a second direction perpendicular to the first direction or along both the first and second directions. 
   
   
       16 . The method of  claim 11 , wherein the openings have an aspect ratio sufficient to trap defects in the crystalline material, and further comprising forming a semiconductor device at least in part in an opening. 
   
   
       17 . The method of  claim 11 , wherein the heating comprises heating at a temperature range independent of a temperature used in the growing a second semiconductor crystalline material. 
   
   
       18 . A method of manufacturing a semiconductor structure comprising:
 epitaxially growing by CVD a first semiconductor crystalline material on a polished surface of a lattice-mismatched semiconductor crystalline material exposed within an opening of an insulator; and   cleaning the polished surface by heating to reduce an oxygen impurity concentration below a prescribed level.   
   
   
       19 . The method of  claim 18 , wherein the first crystalline material is a group IV element or compound including at least one group IV element. 
   
   
       20 . The method of one of  claims 18 , wherein the growing step includes growing strained Ge on a SiGe alloy.