Thermo-electric semiconductor device and method for manufacturing the same

Abstract

A thermo-electric semiconductor device is provided. The thermo-electric semiconductor device includes: a first electrode layer; a spacer layer formed on the first electrode layer and having a plurality of pillars with a uniform height, the plurality of pillars thermally grown and protruded on a surface of the spacer layer; and a second electrode layer formed over the spacer layer in such a manner as to contact tops of the protruded pillars.

1 . A thermo-electric semiconductor device comprising:
 a first electrode layer;   a plurality of pillars with a uniform height, the plurality of pillars formed on the first electrode layer by a semiconductor manufacturing process; and   a second electrode layer formed over the plurality of pillars in such a manner as to contact tops of the plurality of pillars.   
   
   
       2 . The thermo-electric semiconductor device of  claim 1 , further comprising a spacer layer formed on the first electrode layer,
 wherein said plurality of pillars are protruded through the surface of the spacer layer.   
   
   
       3 . The thermo-electric semiconductor device of  claim 2 , wherein said spacer layer is a native oxide layer, and said device further comprises a native oxide layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       4 . The thermo-electric semiconductor device of  claim 2 , wherein said spacer layer is a tunneling enhancing layer and said device further comprises a tunneling enhancing layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       5 . The thermo-electric semiconductor device of  claim 2 , wherein said spacer layer is a work-function reducing layer and said device further comprises a work-function reducing layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       6 . The thermo-electric semiconductor device of  claim 2 , wherein said spacer layer is a radiation reflecting layer and said device further comprises a radiation reflecting layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       7 . A thermo-electric semiconductor device comprising:
 a first electrode layer having a plurality of pits thereon;   a plurality of pillars each protruded from a bottom of each pit, the plurality of pillars having a uniform height from the surface of the first electrode layer; and   a second electrode layer, contacting tops of the plurality of pillars.   
   
   
       8 . The thermo-electric semiconductor device of  claim 7 , wherein the plurality of pillars are formed by a semiconductor manufacturing process. 
   
   
       9 . The thermo-electric semiconductor device of  claim 7 , further comprising a spacer layer on a surface of the first electrode layer facing the second electrode layer. 
   
   
       10 . The thermo-electric semiconductor device of  claim 9 , wherein said spacer layer is a native oxide layer and said device further comprises a native oxide layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       11 . The thermo-electric semiconductor device of  claim 9 , wherein said spacer layer is a tunneling enhancing layer and said device further comprises a tunneling enhancing layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       12 . The thermo-electric semiconductor device of  claim 9 , wherein said spacer layer is a work-function reducing layer and said device further comprises a work-function reducing layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       13 . The thermo-electric semiconductor device of  claim 9 , wherein said spacer layer is a radiation reflecting layer and said device further comprises a radiation reflecting layer on the surface of the second electrode layer that is to contact the plurality of pillars on the first electrode layer. 
   
   
       14 . A thermo-electric semiconductor device comprising:
 a first electrode layer;   a second electrode layer; and   a plurality of pillars disposed between the first electrode layer and the second electrode layer, wherein said plurality of the pillars each is formed on either said first electrode layer or said second electrode layer by a semiconductor manufacturing process;   
   
   
       15 . The thermo-electric semiconductor device of  claim 14 , wherein the first electrode layer has a plurality of pits thereon, and each pillar is protruded from a bottom of each pit. 
   
   
       16 . A method for fabricating a thermo-electric semiconductor device, comprising:
 preparing a first electrode layer;   forming an oxide layer on the first electrode layer;   forming a mask pattern on the oxide layer;   thermally growing the oxide layer selectively using the mask pattern to form a plurality of pillars; and   bonding a second electrode layer to each of tops of the plurality of pillars.   
   
   
       17 . The method of  claim 16 , before the bonding of the second electrode layer, further comprising forming an adhesion layer on a surface of the second electrode layer that is to be bonded to each of the tops of the plurality of pillars. 
   
   
       18 . A method for fabricating a thermo-electric semiconductor device, comprising:
 preparing a first electrode layer;   forming a plurality of spacer regions penetrated into the first electrode layer;   selectively etching a portion of the spacer regions to form a plurality of pillars; and   bonding a second electrode layer to each of tops of the plurality of pillars.   
   
   
       19 . The method of  claim 18 , wherein the forming of the plurality of spacer regions comprising:
 forming a spacer layer on the first electrode layer;   thermally growing the spacer layer selectively into and above the first electrode layer, using a mask pattern; and   removing the remaining spacer layer except for a portion of the spacer layer grown in the direction of the first electrode layer.   
   
   
       20 . The method of  claim 18  before the bonding of the second electrode layer, further comprising forming an adhesion layer on a surface of the second electrode layer that is to be bonded to each of the tops of the plurality of pillars.