Embedded-dram dsp architecture having improved instruction set

Abstract

An embedded-DRAM processor architecture includes a DRAM array, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. A pipelined data assembly approach allowing the functional units to perform register-to-register operations, and allowing the data assembly unit to perform all load/store operations using wide data busses. Data masking and switching hardware allows individual data words or groups of words to be transferred between the registers and memory. Other aspects of the disclosure include a memory and logic structure and an associated method to extract data blocks from memory to accelerate, for example, operations related to image compression and decompression.

1 . An embedded-DRAM (dynamic random access memory) processing system comprising:
 an embedded processor comprising one or more functional units;   a DRAM array comprising a plurality of memory cells arranged in rows and columns;   a row address register configured to store a pointer that references a row of the DRAM array; and   one or more dual-port register files, wherein each dual-port register file comprises a plurality of data registers, and wherein each dual-port register file comprises:
 a first port configured to parallely transfer data between a selected dual-port register file and the referenced row; and 
 a second port configured to transfer data between the selected dual-port register file and one of the functional units. 
   
   
   
       2 . The embedded-DRAM processing system of  claim 1 , wherein each dual-port register file comprises at least one dual-port static random access memory (SRAM) cell. 
   
   
       3 . The embedded-DRAM processing system of  claim 1 , wherein each of the dual-port register files is capable of loading data from or storing data to the entire referenced row of the DRAM array in a single operation. 
   
   
       4 . The embedded-DRAM processing system of  claim 3 , comprising an instruction set comprising:
 a first command for performing an arithmetic operation on the row address register;   a second command for activating the row referenced by the pointer;   a third command for deactivating the row referenced by the pointer subsequent to the referenced row being activated by the second command; and   a fourth command for loading data from selected columns of the entire activated row into a set of data registers of one of the one or more dual-port register files in a single operation.   
   
   
       5 . A method for loading data, comprising:
 using a pointer stored in a row address register to identify a row of a DRAM array;   issuing a first command to activate the row referenced by the pointer;   selecting a set of columns within the activated row using a bit mask;   issuing a second command to cause data stored in the selected set of columns of the activated row to be loaded into a set of data registers within a register file in a single operation; and   issuing a third command to deactivate the activated row.   
   
   
       6 . The method of  claim 5 , wherein activating the referenced row comprises precharging the referenced row. 
   
   
       7 . The method of  claim 5 , comprising issuing a fourth command for performing an arithmetic operation on the row address register. 
   
   
       8 . The method of  claim 5 , comprising issuing a fifth command for manipulating bits in the bit mask. 
   
   
       9 . The method of  claim 5 , comprising issuing a sixth command to toggle the register file between an active state and an inactive state based at least partially upon whether data stored in the register file is being assembled by a data assembly unit. 
   
   
       10 . The method of  claim 5 , wherein the second command causes the entire activated row to be loaded into the set of data register when every column of the activated row is selected by the bit mask. 
   
   
       11 . A data processing device, comprising:
 a DRAM array comprising a plurality of memory cells arranged in rows and columns;   first and second register files each comprising a plurality of data registers, wherein each of the first and second register files is capable of storing an entire row of the DRAM array in response in response to a single command, and wherein each of the first and second register files is capable of entering an active state and an inactive state;   a set of functional units configured to perform logical operations on data accessed from the first register file when the first register file is in the active state and from the second register file when the second register file is in the active state; and   an instruction set comprising:
 a first command to load data from selected columns of an entire selected row of the DRAM array into a set of data registers of one of either the first or second register files in a single operation; and 
 a second command for toggling each of the first and second register files between the active state and the inactive state. 
   
   
   
       12 . The data processing device of  claim 11 , wherein the execution of the second command causes the first register file to toggle from the inactive state to the active state, and causes the second register file to toggle from the active state to the inactive state. 
   
   
       13 . The data processing device of  claim 11 , comprising a data assembly unit configured to assemble data stored in the first and second register files:
 wherein the first register file is determined to be in the inactive state if data stored within the first register file is being assembled by the data assembly unit, and to be in the active state when the data assembly unit completes assembling the data stored within the first register file; and   wherein the second register file is determined to be in the inactive state if data stored within the second register file is being assembled by the data assembly unit, and to be in the active state when the data assembly unit completes assembling the data stored within the second register file.   
   
   
       14 . The data processing device of  claim 13 , wherein the data assembly unit comprises an instruction register configured to receive a first set of instructions from a main instruction stream of a processor, and a second set of instructions from an execution thread stored in program memory. 
   
   
       15 . The data processing device of  claim 13 , wherein the data assembly unit comprises:
 a mask register; and   a mask logic unit configured to manipulate data in the mask register, wherein the information stored in the mask register is output from the data assembly unit via a control line.   
   
   
       16 . The data processing device of  claim 15 , comprising a mask and switch unit configured to receive the mask register information via the control line and to select a set of data registers from either the first register file or the second register by manipulating bits of a bit mask using the received mask register information. 
   
   
       17 . The data processing device of  claim 16 , wherein the first command causes the entire selected row of the DRAM array to be loaded into the set of data registers in a single operation when all columns of the selected row are selected by the bit mask. 
   
   
       18 . The data processing device of  claim 17 , wherein the instruction set comprises a third command for manipulating the bits in the bit mask. 
   
   
       19 . The data processing device of  claim 11 , wherein the set of functional units comprises:
 a dispatch unit configured to dispatch one or more instruction streams; and   a plurality of functional units each being configured to execute a respective one of the one or more instruction streams dispatched by the dispatch unit.   
   
   
       20 . An embedded-DRAM (dynamic random access memory) processing device comprising:
 a DRAM array comprising a plurality of memory cells arranged in rows and columns;   a row address register configured to store a pointer that references a row of the DRAM array;   one or more register files, wherein each register file comprises a plurality of data registers, and wherein each register file is capable of storing an entire row of the DRAM array in response in response to a single command; and   an instruction set comprising:
 a first command for performing an arithmetic operation on the row address register; 
 a second command for activating the row referenced by the pointer; 
 a third command for deactivating the row referenced by the pointer subsequent to the referenced row being activated by the second command; and 
 a fourth command for loading data from selected columns of the entire activated row into a set of data registers of a register file in a single operation. 
   
   
   
       21 . The embedded-DRAM processing device of  claim 20 , wherein activating the referenced row comprises precharging the referenced row. 
   
   
       22 . The embedded-DRAM processing device of  claim 20 , wherein the selected columns are selected based upon the state of a plurality of bits within a bit mask. 
   
   
       23 . The embedded-DRAM processing device of  claim 22 , wherein the fourth command causes the entire activated row to be loaded into the set of data registers when all columns of the activated row are selected by the bit mask. 
   
   
       24 . The embedded-DRAM processing device of  claim 20 , wherein the one or more register files comprises a first register file being in an active state and a second register file being in an inactive state. 
   
   
       25 . The embedded-DRAM processing device of  claim 24 , comprising:
 a first functional unit configured to execute a fifth command for processing the contents of a data register within the active register file; and   a second functional unit configured to execute a sixth command for parallely transferring data between the inactive register file and the DRAM array.   
   
   
       26 . The embedded-DRAM processing device of  claim 25 , wherein the fifth and sixth commands are executed substantially contemporaneously.